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| author |   Huang Ying <ying.huang@intel.com> | 2010-06-08 14:09:10 +0800 |
|---|---|---|
| committer |   H. Peter Anvin <hpa@zytor.com> | 2010-06-10 21:27:36 -0700 |
| commit | 3c417588603e5411f29d22a40f3b5ff71529a4f0 (patch) | |
| tree | ff76c0cbaf48233e1e2ffb35c97b605b88144372 /arch/x86/include/asm/mce.h | |
| parent | x86, mce: Rename MSR_IA32_MCx_CTL2 value (diff) | |
| download | linux-dev-3c417588603e5411f29d22a40f3b5ff71529a4f0.tar.xz linux-dev-3c417588603e5411f29d22a40f3b5ff71529a4f0.zip | |
x86, mce: Fix MSR_IA32_MCI_CTL2 CMCI threshold setup
It is reported that CMCI is not raised when number of corrected error
reaches preset threshold. After inspection, it is found that
MSR_IA32_MCI_CTL2 threshold field is not setup properly. This patch
fixed it.
Value of MCI_CTL2_CMCI_THRESHOLD_MASK is fixed according to x86_64
Software Developer's Manual too.
Reported-by: Shaohui Zheng <shaohui.zheng@intel.com>
Signed-off-by: Huang Ying <ying.huang@intel.com>
LKML-Reference: <1275977350.3444.660.camel@yhuang-dev.sh.intel.com>
Reviewed-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Diffstat (limited to 'arch/x86/include/asm/mce.h')
| -rw-r--r-- | arch/x86/include/asm/mce.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 82db1d8f064b..c62c13cb9788 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -40,7 +40,7 @@ /* CTL2 register defines */ #define MCI_CTL2_CMCI_EN (1ULL << 30) -#define MCI_CTL2_CMCI_THRESHOLD_MASK 0xffffULL +#define MCI_CTL2_CMCI_THRESHOLD_MASK 0x7fffULL #define MCJ_CTX_MASK 3 #define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK) |