diff options
| author |   mike.travis@hpe.com <mike.travis@hpe.com> | 2017-10-12 11:32:02 -0500 |
|---|---|---|
| committer |   Thomas Gleixner <tglx@linutronix.de> | 2017-10-16 22:50:36 +0200 |
| commit | 341102c3ef29c33611586072363cf9982a8bdb77 (patch) | |
| tree | 3eb0e290e32b80153189269f92edf2e187c97a44 /arch/x86/include/asm/tsc.h | |
| parent | x86/timers: Move simple_udelay_calibration() past kvmclock_init() (diff) | |
| download | linux-dev-341102c3ef29c33611586072363cf9982a8bdb77.tar.xz linux-dev-341102c3ef29c33611586072363cf9982a8bdb77.zip | |
x86/tsc: Add option that TSC on Socket 0 being non-zero is valid
Add a flag to indicate and process that TSC counters are on chassis
that reset at different times during system startup. Therefore which
TSC ADJUST values should be zero is not predictable.
Signed-off-by: Mike Travis <mike.travis@hpe.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Dimitri Sivanich <dimitri.sivanich@hpe.com>
Reviewed-by: Russ Anderson <russ.anderson@hpe.com>
Reviewed-by: Andrew Banman <andrew.abanman@hpe.com>
Reviewed-by: Peter Zijlstra <peterz@infradead.org>
Cc: Prarit Bhargava <prarit@redhat.com>
Cc: Andrew Banman <andrew.banman@hpe.com>
Cc: Bin Gao <bin.gao@linux.intel.com>
Link: https://lkml.kernel.org/r/20171012163201.944370012@stormcage.americas.sgi.com
Diffstat (limited to 'arch/x86/include/asm/tsc.h')
| -rw-r--r-- | arch/x86/include/asm/tsc.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/x86/include/asm/tsc.h b/arch/x86/include/asm/tsc.h index d0509c75e150..79125f3609c4 100644 --- a/arch/x86/include/asm/tsc.h +++ b/arch/x86/include/asm/tsc.h @@ -36,11 +36,13 @@ extern void tsc_init(void); extern void mark_tsc_unstable(char *reason); extern int unsynchronized_tsc(void); extern int check_tsc_unstable(void); +extern void mark_tsc_async_resets(char *reason); extern unsigned long native_calibrate_cpu(void); extern unsigned long native_calibrate_tsc(void); extern unsigned long long native_sched_clock_from_tsc(u64 tsc); extern int tsc_clocksource_reliable; +extern bool tsc_async_resets; /* * Boot-time check whether the TSCs are synchronized across |