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| author |   Bin Gao <bin.gao@intel.com> | 2013-10-21 09:16:33 -0700 |
|---|---|---|
| committer |   H. Peter Anvin <hpa@linux.intel.com> | 2014-01-15 22:28:48 -0800 |
| commit | 7da7c1561366ba8adb7275464ab44e84e1faa7e0 (patch) | |
| tree | fbe28621d7961051588dc86f86a90dfe4ecd906f /arch/x86/include/asm/tsc.h | |
| parent | arch: x86: New MailBox support driver for Intel SOC's (diff) | |
| download | linux-dev-7da7c1561366ba8adb7275464ab44e84e1faa7e0.tar.xz linux-dev-7da7c1561366ba8adb7275464ab44e84e1faa7e0.zip | |
x86, tsc: Add static (MSR) TSC calibration on Intel Atom SoCs
On SoCs that have the calibration MSRs available, either there is no
PIT, HPET or PMTIMER to calibrate against, or the PIT/HPET/PMTIMER is
driven from the same clock as the TSC, so calibration is redundant and
just slows down the boot.
TSC rate is caculated by this formula:
<maximum core-clock to bus-clock ratio> * <maximum resolved frequency>
The ratio and the resolved frequency ID can be obtained from MSR.
See Intel 64 and IA-32 System Programming Guid section 16.12 and 30.11.5
for details.
Signed-off-by: Bin Gao <bin.gao@intel.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Link: http://lkml.kernel.org/n/tip-rgm7xmg7k6qnjlw3ynkcjsmh@git.kernel.org
Diffstat (limited to 'arch/x86/include/asm/tsc.h')
| -rw-r--r-- | arch/x86/include/asm/tsc.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/x86/include/asm/tsc.h b/arch/x86/include/asm/tsc.h index 235be70d5bb4..57ae63cd6ee2 100644 --- a/arch/x86/include/asm/tsc.h +++ b/arch/x86/include/asm/tsc.h @@ -65,4 +65,7 @@ extern int notsc_setup(char *); extern void tsc_save_sched_clock_state(void); extern void tsc_restore_sched_clock_state(void); +/* MSR based TSC calibration for Intel Atom SoC platforms */ +int try_msr_calibrate_tsc(unsigned long *fast_calibrate); + #endif /* _ASM_X86_TSC_H */ |