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| author |   Alok Kataria <akataria@vmware.com> | 2008-10-31 12:01:58 -0700 |
|---|---|---|
| committer |   H. Peter Anvin <hpa@zytor.com> | 2008-11-01 18:58:01 -0700 |
| commit | eca0cd028bdf0f6aaceb0d023e9c7501079a7dda (patch) | |
| tree | 13a3a723f4e286a617437442138f2a6130502142 /arch/x86/include/asm/vmware.h | |
| parent | x86: Hypervisor detection and get tsc_freq from hypervisor (diff) | |
| download | linux-dev-eca0cd028bdf0f6aaceb0d023e9c7501079a7dda.tar.xz linux-dev-eca0cd028bdf0f6aaceb0d023e9c7501079a7dda.zip | |
x86: Add a synthetic TSC_RELIABLE feature bit.
Impact: Changes timebase calibration on Vmware.
Use the synthetic TSC_RELIABLE bit to workaround virtualization anomalies.
Virtual TSCs can be kept nearly in sync, but because the virtual TSC
offset is set by software, it's not perfect. So, the TSC
synchronization test can fail. Even then the TSC can be used as a
clocksource since the VMware platform exports a reliable TSC to the
guest for timekeeping purposes. Use this bit to check if we need to
skip the TSC sync checks.
Along with this also set the CONSTANT_TSC bit when on VMware, since we
still want to use TSC as clocksource on VM running over hardware which
has unsynchronized TSC's (opteron's), since the hypervisor will take
care of providing consistent TSC to the guest.
Signed-off-by: Alok N Kataria <akataria@vmware.com>
Signed-off-by: Dan Hecht <dhecht@vmware.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Diffstat (limited to 'arch/x86/include/asm/vmware.h')
| -rw-r--r-- | arch/x86/include/asm/vmware.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/include/asm/vmware.h b/arch/x86/include/asm/vmware.h index 02dfea5aebc4..c11b7e100d83 100644 --- a/arch/x86/include/asm/vmware.h +++ b/arch/x86/include/asm/vmware.h @@ -22,5 +22,6 @@ extern unsigned long vmware_get_tsc_khz(void); extern int vmware_platform(void); +extern void vmware_set_feature_bits(struct cpuinfo_x86 *c); #endif |