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authorDavid Woodhouse <dwmw@amazon.co.uk>2020-10-24 22:35:32 +0100
committerThomas Gleixner <tglx@linutronix.de>2020-10-28 20:26:29 +0100
commitab0f59c6f135289c7ea90b0e2471674bf289d884 (patch)
treeda6ae53692af175c9993ff0f372ba543f6af468a /arch/x86/include/asm/x86_init.h
parentx86/ioapic: Handle Extended Destination ID field in RTE (diff)
downloadlinux-dev-ab0f59c6f135289c7ea90b0e2471674bf289d884.tar.xz
linux-dev-ab0f59c6f135289c7ea90b0e2471674bf289d884.zip
x86/apic: Support 15 bits of APIC ID in MSI where available
Some hypervisors can allow the guest to use the Extended Destination ID field in the MSI address to address up to 32768 CPUs. This applies to all downstream devices which generate MSI cycles, including HPET, I/O-APIC and PCI MSI. HPET and PCI MSI use the same __irq_msi_compose_msg() function, while I/O-APIC generates its own and had support for the extended bits added in a previous commit. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20201024213535.443185-33-dwmw2@infradead.org
Diffstat (limited to 'arch/x86/include/asm/x86_init.h')
-rw-r--r--arch/x86/include/asm/x86_init.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/x86/include/asm/x86_init.h b/arch/x86/include/asm/x86_init.h
index dde5b3f1e7cd..5c69f7eb5d47 100644
--- a/arch/x86/include/asm/x86_init.h
+++ b/arch/x86/include/asm/x86_init.h
@@ -116,6 +116,7 @@ struct x86_init_pci {
* @init_platform: platform setup
* @guest_late_init: guest late init
* @x2apic_available: X2APIC detection
+ * @msi_ext_dest_id: MSI supports 15-bit APIC IDs
* @init_mem_mapping: setup early mappings during init_mem_mapping()
* @init_after_bootmem: guest init after boot allocator is finished
*/
@@ -123,6 +124,7 @@ struct x86_hyper_init {
void (*init_platform)(void);
void (*guest_late_init)(void);
bool (*x2apic_available)(void);
+ bool (*msi_ext_dest_id)(void);
void (*init_mem_mapping)(void);
void (*init_after_bootmem)(void);
};