diff options
| author |   Andrew Cooper <andrew.cooper3@citrix.com> | 2022-06-24 14:41:21 +0100 |
|---|---|---|
| committer |   Borislav Petkov <bp@suse.de> | 2022-06-27 10:34:01 +0200 |
| commit | 26aae8ccbc1972233afd08fb3f368947c0314265 (patch) | |
| tree | 707c1db81342922fac0b75877fe4e13084589e3d /arch/x86/include | |
| parent | x86/common: Stamp out the stepping madness (diff) | |
| download | linux-dev-26aae8ccbc1972233afd08fb3f368947c0314265.tar.xz linux-dev-26aae8ccbc1972233afd08fb3f368947c0314265.zip | |
x86/cpu/amd: Enumerate BTC_NO
BTC_NO indicates that hardware is not susceptible to Branch Type Confusion.
Zen3 CPUs don't suffer BTC.
Hypervisors are expected to synthesise BTC_NO when it is appropriate
given the migration pool, to prevent kernels using heuristics.
[ bp: Massage. ]
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Diffstat (limited to 'arch/x86/include')
| -rw-r--r-- | arch/x86/include/asm/cpufeatures.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index d143f018eda1..7e8099fd5ec1 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -322,6 +322,7 @@ #define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */ #define X86_FEATURE_AMD_SSB_NO (13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */ #define X86_FEATURE_CPPC (13*32+27) /* Collaborative Processor Performance Control */ +#define X86_FEATURE_BTC_NO (13*32+29) /* "" Not vulnerable to Branch Type Confusion */ #define X86_FEATURE_BRS (13*32+31) /* Branch Sampling available */ /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */ |