diff options
| author |   Peter Zijlstra <peterz@infradead.org> | 2022-06-24 13:48:58 +0200 |
|---|---|---|
| committer |   Borislav Petkov <bp@suse.de> | 2022-06-27 10:33:59 +0200 |
| commit | 6ad0ad2bf8a67e27d1f9d006a1dabb0e1c360cc3 (patch) | |
| tree | dca4e2dceb16491a3bbc17d5ab1b604d78eeed6c /arch/x86/include | |
| parent | x86/bugs: Split spectre_v2_select_mitigation() and spectre_v2_user_select_mitigation() (diff) | |
| download | linux-dev-6ad0ad2bf8a67e27d1f9d006a1dabb0e1c360cc3.tar.xz linux-dev-6ad0ad2bf8a67e27d1f9d006a1dabb0e1c360cc3.zip | |
x86/bugs: Report Intel retbleed vulnerability
Skylake suffers from RSB underflow speculation issues; report this
vulnerability and it's mitigation (spectre_v2=ibrs).
[jpoimboe: cleanups, eibrs]
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Borislav Petkov <bp@suse.de>
Reviewed-by: Josh Poimboeuf <jpoimboe@kernel.org>
Signed-off-by: Borislav Petkov <bp@suse.de>
Diffstat (limited to 'arch/x86/include')
| -rw-r--r-- | arch/x86/include/asm/msr-index.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index d27e0581b777..059c7e500ab4 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -93,6 +93,7 @@ #define MSR_IA32_ARCH_CAPABILITIES 0x0000010a #define ARCH_CAP_RDCL_NO BIT(0) /* Not susceptible to Meltdown */ #define ARCH_CAP_IBRS_ALL BIT(1) /* Enhanced IBRS support */ +#define ARCH_CAP_RSBA BIT(2) /* RET may use alternative branch predictors */ #define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH BIT(3) /* Skip L1D flush on vmentry */ #define ARCH_CAP_SSB_NO BIT(4) /* * Not susceptible to Speculative Store Bypass |