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| author |   Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> | 2018-04-27 16:34:37 -0500 |
|---|---|---|
| committer |   Thomas Gleixner <tglx@linutronix.de> | 2018-05-06 12:49:15 +0200 |
| commit | 68091ee7ac3c1a8786fe1bebbd616b14236efb99 (patch) | |
| tree | 368d443c105928aba52b17c236f376bf048d8f62 /arch/x86/kernel/cpu/amd.c | |
| parent | x86/CPU: Rename intel_cacheinfo.c to cacheinfo.c (diff) | |
| download | linux-dev-68091ee7ac3c1a8786fe1bebbd616b14236efb99.tar.xz linux-dev-68091ee7ac3c1a8786fe1bebbd616b14236efb99.zip | |
x86/CPU/AMD: Calculate last level cache ID from number of sharing threads
Last Level Cache ID can be calculated from the number of threads sharing
the cache, which is available from CPUID Fn0x8000001D (Cache Properties).
This is used to left-shift the APIC ID to derive LLC ID.
Therefore, default to this method unless the APIC ID enumeration does not
follow the scheme.
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/1524864877-111962-5-git-send-email-suravee.suthikulpanit@amd.com
Diffstat (limited to 'arch/x86/kernel/cpu/amd.c')
| -rw-r--r-- | arch/x86/kernel/cpu/amd.c | 19 |
1 files changed, 3 insertions, 16 deletions
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index a37a83809665..bf27246bb7bd 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -9,6 +9,7 @@ #include <linux/random.h> #include <asm/processor.h> #include <asm/apic.h> +#include <asm/cacheinfo.h> #include <asm/cpu.h> #include <asm/smp.h> #include <asm/pci-direct.h> @@ -343,22 +344,8 @@ static void amd_get_topology(struct cpuinfo_x86 *c) c->x86_max_cores /= smp_num_siblings; } - /* - * We may have multiple LLCs if L3 caches exist, so check if we - * have an L3 cache by looking at the L3 cache CPUID leaf. - */ - if (cpuid_edx(0x80000006)) { - if (c->x86 == 0x17) { - /* - * LLC is at the core complex level. - * Core complex id is ApicId[3]. - */ - per_cpu(cpu_llc_id, cpu) = c->apicid >> 3; - } else { - /* LLC is at the node level. */ - per_cpu(cpu_llc_id, cpu) = node_id; - } - } + cacheinfo_amd_init_llc_id(c, cpu, node_id); + } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { u64 value; |