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| author |   Yazen Ghannam <Yazen.Ghannam@amd.com> | 2016-09-12 09:59:36 +0200 |
|---|---|---|
| committer |   Thomas Gleixner <tglx@linutronix.de> | 2016-09-13 15:23:11 +0200 |
| commit | 66ef269dbbe45e264ccf7146d5db32b04478d148 (patch) | |
| tree | 1df3fe0b67de72666ad2056e10882049efa58c20 /arch/x86/kernel/cpu/mcheck/mce_amd.c | |
| parent | x86/mce/AMD: Update sysfs bank names for SMCA systems (diff) | |
| download | linux-dev-66ef269dbbe45e264ccf7146d5db32b04478d148.tar.xz linux-dev-66ef269dbbe45e264ccf7146d5db32b04478d148.zip | |
x86/mce/AMD: Ensure the deferred error interrupt is of type APIC on SMCA systems
The Deferred Error Interrupt Type is set per bank on Scalable MCA
systems. This is done in a bitfield in the MCA_CONFIG register of each
bank. We should set its type to APIC-based interrupt and not assume BIOS
has set it for us.
Signed-off-by: Yazen Ghannam <Yazen.Ghannam@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: http://lkml.kernel.org/r/1472737486-1720-1-git-send-email-Yazen.Ghannam@amd.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/x86/kernel/cpu/mcheck/mce_amd.c')
| -rw-r--r-- | arch/x86/kernel/cpu/mcheck/mce_amd.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c index 0f9d0786bc97..16766e09c2b7 100644 --- a/arch/x86/kernel/cpu/mcheck/mce_amd.c +++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c @@ -463,6 +463,20 @@ prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, */ smca_high &= ~BIT(2); + /* + * SMCA sets the Deferred Error Interrupt type per bank. + * + * MCA_CONFIG[DeferredIntTypeSupported] is bit 5, and tells us + * if the DeferredIntType bit field is available. + * + * MCA_CONFIG[DeferredIntType] is bits [38:37] ([6:5] in the + * high portion of the MSR). OS should set this to 0x1 to enable + * APIC based interrupt. First, check that no interrupt has been + * set. + */ + if ((smca_low & BIT(5)) && !((smca_high >> 5) & 0x3)) + smca_high |= BIT(5); + wrmsr(smca_addr, smca_low, smca_high); } |