diff options
| author |   Kan Liang <kan.liang@linux.intel.com> | 2022-08-18 11:44:29 -0700 |
|---|---|---|
| committer |   Peter Zijlstra <peterz@infradead.org> | 2022-08-19 19:47:31 +0200 |
| commit | cde643ff75bc20c538dfae787ca3b587bab16b50 (patch) | |
| tree | b8446799f7917aae5d75a30c615b2aa386ec14ee /arch/x86 | |
| parent | perf/x86/intel/ds: Fix precise store latency handling (diff) | |
| download | linux-dev-cde643ff75bc20c538dfae787ca3b587bab16b50.tar.xz linux-dev-cde643ff75bc20c538dfae787ca3b587bab16b50.zip | |
perf/x86/intel: Fix pebs event constraints for ADL
According to the latest event list, the LOAD_LATENCY PEBS event only
works on the GP counter 0 and 1 for ADL and RPL.
Update the pebs event constraints table.
Fixes: f83d2f91d259 ("perf/x86/intel: Add Alder Lake Hybrid support")
Reported-by: Ammy Yi <ammy.yi@intel.com>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: stable@vger.kernel.org
Link: https://lkml.kernel.org/r/20220818184429.2355857-1-kan.liang@linux.intel.com
Diffstat (limited to 'arch/x86')
| -rw-r--r-- | arch/x86/events/intel/ds.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index e5b587499122..de1f55d51784 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -830,7 +830,7 @@ struct event_constraint intel_glm_pebs_event_constraints[] = { struct event_constraint intel_grt_pebs_event_constraints[] = { /* Allow all events as PEBS with no flags */ - INTEL_HYBRID_LAT_CONSTRAINT(0x5d0, 0xf), + INTEL_HYBRID_LAT_CONSTRAINT(0x5d0, 0x3), INTEL_HYBRID_LAT_CONSTRAINT(0x6d0, 0xf), EVENT_CONSTRAINT_END }; |