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authorDmitry Torokhov <dmitry.torokhov@gmail.com>2019-07-20 07:07:56 +0300
committerDmitry Torokhov <dmitry.torokhov@gmail.com>2019-07-20 07:07:56 +0300
commitc39f2d9db0fd81ea20bb5cce9b3f082ca63753e2 (patch)
tree8e80ed5601b4fb8880a2ca8e08802bc8b1f850bd /arch/xtensa/include/asm/cache.h
parentMerge branch 'next' into for-linus (diff)
parentInput: alps - fix a mismatch between a condition check and its comment (diff)
downloadlinux-dev-c39f2d9db0fd81ea20bb5cce9b3f082ca63753e2.tar.xz
linux-dev-c39f2d9db0fd81ea20bb5cce9b3f082ca63753e2.zip
Merge branch 'next' into for-linus
Prepare second round of input updates for 5.3 merge window.
Diffstat (limited to 'arch/xtensa/include/asm/cache.h')
-rw-r--r--arch/xtensa/include/asm/cache.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/xtensa/include/asm/cache.h b/arch/xtensa/include/asm/cache.h
index d2fd932fdb4d..b21fd133ff62 100644
--- a/arch/xtensa/include/asm/cache.h
+++ b/arch/xtensa/include/asm/cache.h
@@ -11,7 +11,7 @@
#ifndef _XTENSA_CACHE_H
#define _XTENSA_CACHE_H
-#include <variant/core.h>
+#include <asm/core.h>
#define L1_CACHE_SHIFT XCHAL_DCACHE_LINEWIDTH
#define L1_CACHE_BYTES XCHAL_DCACHE_LINESIZE