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| author |   Max Filippov <jcmvbkbc@gmail.com> | 2018-08-12 06:01:40 -0700 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2018-08-13 20:08:19 -0700 |
| commit | 7bb516ca5424e12b42124fab2906b6da9c81ba9c (patch) | |
| tree | 275dd23356eba62a81025221e23df3210a87a7be /arch/xtensa/kernel/head.S | |
| parent | xtensa: increase ranges in ___invalidate_{i,d}cache_all (diff) | |
| download | linux-dev-7bb516ca5424e12b42124fab2906b6da9c81ba9c.tar.xz linux-dev-7bb516ca5424e12b42124fab2906b6da9c81ba9c.zip | |
xtensa: rework noMMU cache attributes initialization
Marking default memory region as cached is not always sufficient and is
not flexible. Allow specifying cache attributes for the whole memory
address space with new config entry MEMMAP_CACHEATTR. Apply it after
cache initialization.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'arch/xtensa/kernel/head.S')
| -rw-r--r-- | arch/xtensa/kernel/head.S | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/xtensa/kernel/head.S b/arch/xtensa/kernel/head.S index 9c4e9433e536..2f76118ecf62 100644 --- a/arch/xtensa/kernel/head.S +++ b/arch/xtensa/kernel/head.S @@ -181,6 +181,8 @@ ENTRY(_startup) isync + initialize_cacheattr + #ifdef CONFIG_HAVE_SMP movi a2, CCON # MX External Register to Configure Cache movi a3, 1 |