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| author |   Paul Burton <paul.burton@imgtec.com> | 2015-07-09 10:40:41 +0100 |
|---|---|---|
| committer |   Ralf Baechle <ralf@linux-mips.org> | 2015-07-10 11:02:20 +0200 |
| commit | 1e18ac7aeaec357048172695b1fbb461205b166f (patch) | |
| tree | 8e4e1c279276c34e4e5f06b56426f2dbe249f20c /arch | |
| parent | MIPS: Pistachio: Support CDMM & Fast Debug Channel (diff) | |
| download | linux-dev-1e18ac7aeaec357048172695b1fbb461205b166f.tar.xz linux-dev-1e18ac7aeaec357048172695b1fbb461205b166f.zip | |
MIPS: c-r4k: Extend way_string array
The L2 cache in the I6400 core has 16 ways, so extend the way_string
array to take such caches into account.
[ralf@linux-mips.org: Other already supported CPUs are free to support
more than 8 ways of cache as well.]
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10640/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/mips/mm/c-r4k.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index a5974ddba44b..fbea4432f3f2 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -945,7 +945,9 @@ static void b5k_instruction_hazard(void) } static char *way_string[] = { NULL, "direct mapped", "2-way", - "3-way", "4-way", "5-way", "6-way", "7-way", "8-way" + "3-way", "4-way", "5-way", "6-way", "7-way", "8-way", + "9-way", "10-way", "11-way", "12-way", + "13-way", "14-way", "15-way", "16-way", }; static void probe_pcache(void) |