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authorSuzuki Poulose <suzuki@in.ibm.com>2011-12-14 22:57:57 +0000
committerJosh Boyer <jwboyer@gmail.com>2011-12-20 10:20:38 -0500
commit239132454583d474932d8835f87a244f6f1bff9e (patch)
treea7c5730d7170270ebf6250a6d19ef484998a4853 /arch
parentpowerpc: Rename mapping based RELOCATABLE to DYNAMIC_MEMSTART for BookE (diff)
downloadlinux-dev-239132454583d474932d8835f87a244f6f1bff9e.tar.xz
linux-dev-239132454583d474932d8835f87a244f6f1bff9e.zip
powerpc/44x: Enable DYNAMIC_MEMSTART for 440x
DYNAMIC_MEMSTART(old RELOCATABLE) was restricted only to PPC_47x variants of 44x. This patch enables DYNAMIC_MEMSTART for 440x based chipsets. Signed-off-by: Suzuki K. Poulose <suzuki@in.ibm.com> Cc: Josh Boyer <jwboyer@gmail.com> Cc: Kumar Gala <galak@kernel.crashing.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: linux ppc dev <linuxppc-dev@lists.ozlabs.org> Signed-off-by: Josh Boyer <jwboyer@gmail.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/Kconfig2
-rw-r--r--arch/powerpc/kernel/head_44x.S12
2 files changed, 13 insertions, 1 deletions
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 6c8475692322..8b323b7b0a61 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -833,7 +833,7 @@ config LOWMEM_CAM_NUM
config DYNAMIC_MEMSTART
bool "Enable page aligned dynamic load address for kernel (EXPERIMENTAL)"
- depends on EXPERIMENTAL && ADVANCED_OPTIONS && FLATMEM && (FSL_BOOKE || PPC_47x)
+ depends on EXPERIMENTAL && ADVANCED_OPTIONS && FLATMEM && (FSL_BOOKE || 44x)
select NONSTATIC_KERNEL
help
This option enables the kernel to be loaded at any page aligned
diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S
index d7a1debda10b..0878bf5d8a68 100644
--- a/arch/powerpc/kernel/head_44x.S
+++ b/arch/powerpc/kernel/head_44x.S
@@ -804,12 +804,24 @@ skpinv: addi r4,r4,1 /* Increment */
/*
* Configure and load pinned entry into TLB slot 63.
*/
+#ifdef CONFIG_DYNAMIC_MEMSTART
+
+ /* Read the XLAT entry for our current mapping */
+ tlbre r25,r23,PPC44x_TLB_XLAT
+
+ lis r3,KERNELBASE@h
+ ori r3,r3,KERNELBASE@l
+
+ /* Use our current RPN entry */
+ mr r4,r25
+#else
lis r3,PAGE_OFFSET@h
ori r3,r3,PAGE_OFFSET@l
/* Kernel is at the base of RAM */
li r4, 0 /* Load the kernel physical address */
+#endif
/* Load the kernel PID = 0 */
li r0,0