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| author |   Paul Mundt <lethal@linux-sh.org> | 2007-11-10 20:25:28 +0900 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2008-01-28 13:18:43 +0900 |
| commit | 27a511c6f37c05c5cf8fae9fe513f60d87af9158 (patch) | |
| tree | 1a4832642070fb7663d59900e578e575974c51f0 /arch | |
| parent | sh: Don't reference UBC code in CPU init on sh64. (diff) | |
| download | linux-dev-27a511c6f37c05c5cf8fae9fe513f60d87af9158.tar.xz linux-dev-27a511c6f37c05c5cf8fae9fe513f60d87af9158.zip | |
sh: Disable initial cache flush on SH-5.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/sh/kernel/cpu/init.c | 32 |
1 files changed, 18 insertions, 14 deletions
diff --git a/arch/sh/kernel/cpu/init.c b/arch/sh/kernel/cpu/init.c index f37f1c031631..fd1688e6c61c 100644 --- a/arch/sh/kernel/cpu/init.c +++ b/arch/sh/kernel/cpu/init.c @@ -63,24 +63,11 @@ static void __init speculative_execution_init(void) /* * Generic first-level cache init */ +#ifdef CONFIG_SUPERH32 static void __init cache_init(void) { unsigned long ccr, flags; - /* First setup the rest of the I-cache info */ - current_cpu_data.icache.entry_mask = current_cpu_data.icache.way_incr - - current_cpu_data.icache.linesz; - - current_cpu_data.icache.way_size = current_cpu_data.icache.sets * - current_cpu_data.icache.linesz; - - /* And the D-cache too */ - current_cpu_data.dcache.entry_mask = current_cpu_data.dcache.way_incr - - current_cpu_data.dcache.linesz; - - current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets * - current_cpu_data.dcache.linesz; - jump_to_P2(); ccr = ctrl_inl(CCR); @@ -160,6 +147,9 @@ static void __init cache_init(void) ctrl_outl(flags, CCR); back_to_P1(); } +#else +#define cache_init() do { } while (0) +#endif #ifdef CONFIG_SH_DSP static void __init release_dsp(void) @@ -230,6 +220,20 @@ asmlinkage void __cpuinit sh_cpu_init(void) if (current_cpu_data.type == CPU_SH_NONE) panic("Unknown CPU"); + /* First setup the rest of the I-cache info */ + current_cpu_data.icache.entry_mask = current_cpu_data.icache.way_incr - + current_cpu_data.icache.linesz; + + current_cpu_data.icache.way_size = current_cpu_data.icache.sets * + current_cpu_data.icache.linesz; + + /* And the D-cache too */ + current_cpu_data.dcache.entry_mask = current_cpu_data.dcache.way_incr - + current_cpu_data.dcache.linesz; + + current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets * + current_cpu_data.dcache.linesz; + /* Init the cache */ cache_init(); |