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authorWill Deacon <will.deacon@arm.com>2018-02-05 15:34:16 +0000
committerCatalin Marinas <catalin.marinas@arm.com>2018-02-06 22:53:28 +0000
commit669474e772b952b14f4de4845a1558fd4c0414a4 (patch)
tree95e11d01c1c6eb07b25fbc271dc90222718a3c8e /arch
parentarm64: idmap: Use "awx" flags for .idmap.text .pushsection directives (diff)
downloadlinux-dev-669474e772b952b14f4de4845a1558fd4c0414a4.tar.xz
linux-dev-669474e772b952b14f4de4845a1558fd4c0414a4.zip
arm64: barrier: Add CSDB macros to control data-value prediction
For CPUs capable of data value prediction, CSDB waits for any outstanding predictions to architecturally resolve before allowing speculative execution to continue. Provide macros to expose it to the arch code. Reviewed-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm64/include/asm/assembler.h7
-rw-r--r--arch/arm64/include/asm/barrier.h1
2 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h
index 544878a9f29e..1f44b4255a28 100644
--- a/arch/arm64/include/asm/assembler.h
+++ b/arch/arm64/include/asm/assembler.h
@@ -116,6 +116,13 @@
.endm
/*
+ * Value prediction barrier
+ */
+ .macro csdb
+ hint #20
+ .endm
+
+/*
* NOP sequence
*/
.macro nops, num
diff --git a/arch/arm64/include/asm/barrier.h b/arch/arm64/include/asm/barrier.h
index 77651c49ef44..c0a846d2c602 100644
--- a/arch/arm64/include/asm/barrier.h
+++ b/arch/arm64/include/asm/barrier.h
@@ -32,6 +32,7 @@
#define dsb(opt) asm volatile("dsb " #opt : : : "memory")
#define psb_csync() asm volatile("hint #17" : : : "memory")
+#define csdb() asm volatile("hint #20" : : : "memory")
#define mb() dsb(sy)
#define rmb() dsb(ld)