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| author |   Ralf Baechle <ralf@linux-mips.org> | 2007-05-31 14:03:45 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2007-06-11 18:20:54 +0100 |
| commit | 6a05888d713dd915d3268000a479e38646aa423f (patch) | |
| tree | ade4e4ac2ff5c77a182ec10cd7aa2586c38a7411 /arch | |
| parent | [MIPS] SMTC: Don't continue in set_vi_srs_handler on detected bad arguments. (diff) | |
| download | linux-dev-6a05888d713dd915d3268000a479e38646aa423f.tar.xz linux-dev-6a05888d713dd915d3268000a479e38646aa423f.zip | |
[MIPS] SMTC: The MT ASE requires to initialize c0_pagemask and c0_wired.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/mips/kernel/traps.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 44f0a2c11807..a7a17eb9bfcd 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1384,6 +1384,13 @@ void __init per_cpu_trap_init(void) cpu_cache_init(); tlb_init(); #ifdef CONFIG_MIPS_MT_SMTC + } else if (!secondaryTC) { + /* + * First TC in non-boot VPE must do subset of tlb_init() + * for MMU countrol registers. + */ + write_c0_pagemask(PM_DEFAULT_MASK); + write_c0_wired(0); } #endif /* CONFIG_MIPS_MT_SMTC */ } |