diff options
| author |   Hauke Mehrtens <hauke.mehrtens@lantiq.com> | 2015-10-28 23:37:32 +0100 |
|---|---|---|
| committer |   Ralf Baechle <ralf@linux-mips.org> | 2015-11-11 08:37:05 +0100 |
| commit | b5a03d0cb32c35f7ca9a042f01c1de14daaeeb11 (patch) | |
| tree | ed3a5b4c67aed44d9addf08bcac2a141d0de941a /arch | |
| parent | MIPS: Lantiq: Add support for setting PMU register on AR10 and GRX390 (diff) | |
| download | linux-dev-b5a03d0cb32c35f7ca9a042f01c1de14daaeeb11.tar.xz linux-dev-b5a03d0cb32c35f7ca9a042f01c1de14daaeeb11.zip | |
MIPS: Lantiq: Rename CGU_SYS_VR9 register
This register is also used on other SoCs.
Signed-off-by: Hauke Mehrtens <hauke.mehrtens@lantiq.com>
Acked-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11383/
Patchwork: https://patchwork.linux-mips.org/patch/11397/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/mips/lantiq/xway/clk.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/arch/mips/lantiq/xway/clk.c b/arch/mips/lantiq/xway/clk.c index 8750dc0a1bf6..55fd1508fb11 100644 --- a/arch/mips/lantiq/xway/clk.c +++ b/arch/mips/lantiq/xway/clk.c @@ -4,6 +4,7 @@ * by the Free Software Foundation. * * Copyright (C) 2010 John Crispin <blogic@openwrt.org> + * Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG */ #include <linux/io.h> @@ -25,8 +26,8 @@ static unsigned int ram_clocks[] = { /* legacy xway clock */ #define CGU_SYS 0x10 -/* vr9 clock */ -#define CGU_SYS_VR9 0x0c +/* vr9, ar10/grx390 clock */ +#define CGU_SYS_XRX 0x0c #define CGU_IF_CLK_VR9 0x24 unsigned long ltq_danube_fpi_hz(void) @@ -104,7 +105,7 @@ unsigned long ltq_vr9_cpu_hz(void) unsigned int cpu_sel; unsigned long clk; - cpu_sel = (ltq_cgu_r32(CGU_SYS_VR9) >> 4) & 0xf; + cpu_sel = (ltq_cgu_r32(CGU_SYS_XRX) >> 4) & 0xf; switch (cpu_sel) { case 0: @@ -145,7 +146,7 @@ unsigned long ltq_vr9_fpi_hz(void) unsigned long clk; cpu_clk = ltq_vr9_cpu_hz(); - ocp_sel = ltq_cgu_r32(CGU_SYS_VR9) & 0x3; + ocp_sel = ltq_cgu_r32(CGU_SYS_XRX) & 0x3; switch (ocp_sel) { case 0: |