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| author |   Russell King <rmk+kernel@arm.linux.org.uk> | 2014-06-20 11:23:02 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2014-06-20 11:23:02 +0100 |
| commit | b8d8772e53f83cc87aeeab1c3a60d5d5d45ce38b (patch) | |
| tree | 7b9fbf10b6e055329b507e6630d763ce36134da2 /arch | |
| parent | ARM: perf: fix compiler warning with gcc 4.6.4 (and tidy code) (diff) | |
| download | linux-dev-b8d8772e53f83cc87aeeab1c3a60d5d5d45ce38b.tar.xz linux-dev-b8d8772e53f83cc87aeeab1c3a60d5d5d45ce38b.zip | |
ARM: arm925: ensure assembly sets up writethrough mapping
Commit ca8f0b0a545f ("ARM: ensure C page table setup code follows
assembly code") did what it said on the tin, but some of the older
CPU code omitted the default cache policy from their files. This
results in the kernel running with the caches disabled. Fix this
for ARM925.
Reported-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mm/proc-arm925.S | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S index 97448c3acf38..ba0d58e1a2a2 100644 --- a/arch/arm/mm/proc-arm925.S +++ b/arch/arm/mm/proc-arm925.S @@ -502,6 +502,7 @@ __\name\()_proc_info: .long \cpu_val .long \cpu_mask .long PMD_TYPE_SECT | \ + PMD_SECT_CACHEABLE | \ PMD_BIT4 | \ PMD_SECT_AP_WRITE | \ PMD_SECT_AP_READ |