diff options
| author |   Anton Blanchard <anton@samba.org> | 2013-10-15 14:36:31 +1100 |
|---|---|---|
| committer |   Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2013-10-30 16:02:14 +1100 |
| commit | bbe30b3b576b4ba96641a7c244071282618b2cbb (patch) | |
| tree | cdba0447ee45aed62e9ce959906739d0fb058a8d /arch | |
| parent | powerpc: Enable virtio on ppc64 and pseries configs (diff) | |
| download | linux-dev-bbe30b3b576b4ba96641a7c244071282618b2cbb.tar.xz linux-dev-bbe30b3b576b4ba96641a7c244071282618b2cbb.zip | |
powerpc: Use 32 bit loads and stores when operating on condition register values
The condition register (CR) is a 32 bit quantity so we should use
32 bit loads and stores.
Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/powerpc/kernel/tm.S | 8 | ||||
| -rw-r--r-- | arch/powerpc/platforms/powernv/opal-wrappers.S | 4 |
2 files changed, 6 insertions, 6 deletions
diff --git a/arch/powerpc/kernel/tm.S b/arch/powerpc/kernel/tm.S index 761af4f0a632..ef47bcbd4352 100644 --- a/arch/powerpc/kernel/tm.S +++ b/arch/powerpc/kernel/tm.S @@ -106,7 +106,7 @@ DSCR_DEFAULT: _GLOBAL(tm_reclaim) mfcr r6 mflr r0 - std r6, 8(r1) + stw r6, 8(r1) std r0, 16(r1) std r2, 40(r1) stdu r1, -TM_FRAME_SIZE(r1) @@ -285,7 +285,7 @@ dont_backup_fp: REST_NVGPRS(r1) addi r1, r1, TM_FRAME_SIZE - ld r4, 8(r1) + lwz r4, 8(r1) ld r0, 16(r1) mtcr r4 mtlr r0 @@ -310,7 +310,7 @@ dont_backup_fp: _GLOBAL(tm_recheckpoint) mfcr r5 mflr r0 - std r5, 8(r1) + stw r5, 8(r1) std r0, 16(r1) std r2, 40(r1) stdu r1, -TM_FRAME_SIZE(r1) @@ -444,7 +444,7 @@ restore_gprs: REST_NVGPRS(r1) addi r1, r1, TM_FRAME_SIZE - ld r4, 8(r1) + lwz r4, 8(r1) ld r0, 16(r1) mtcr r4 mtlr r0 diff --git a/arch/powerpc/platforms/powernv/opal-wrappers.S b/arch/powerpc/platforms/powernv/opal-wrappers.S index 2a03e1e63c7a..403d05840625 100644 --- a/arch/powerpc/platforms/powernv/opal-wrappers.S +++ b/arch/powerpc/platforms/powernv/opal-wrappers.S @@ -24,7 +24,7 @@ mflr r0; \ mfcr r12; \ std r0,16(r1); \ - std r12,8(r1); \ + stw r12,8(r1); \ std r1,PACAR1(r13); \ li r0,0; \ mfmsr r12; \ @@ -53,7 +53,7 @@ _STATIC(opal_return) */ FIXUP_ENDIAN ld r2,PACATOC(r13); - ld r4,8(r1); + lwz r4,8(r1); ld r5,16(r1); ld r6,PACASAVEDMSR(r13); mtspr SPRN_SRR0,r5; |