diff options
| author |   Andi Kleen <ak@suse.de> | 2007-05-21 14:31:47 +0200 |
|---|---|---|
| committer |   Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-05-21 09:56:57 -0700 |
| commit | c12ceb766eb5ac975c1145d51236fcdcf81a6578 (patch) | |
| tree | ecc1e605973e3877b99a45c858f57d5a4ceea1be /arch | |
| parent | x86_64: Support gcc 5 properly (diff) | |
| download | linux-dev-c12ceb766eb5ac975c1145d51236fcdcf81a6578.tar.xz linux-dev-c12ceb766eb5ac975c1145d51236fcdcf81a6578.zip | |
i386: Clear MCE flag on AMD K6
It reports machine check capability in CPUID, but doesn't actually
implement all the necessary MSRs of the standard Intel machine
check architecture.
This fixes a boot failure on K6s recently introduced.
Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/i386/kernel/cpu/amd.c | 4 | ||||
| -rw-r--r-- | arch/i386/kernel/cpu/mcheck/k7.c | 6 |
2 files changed, 7 insertions, 3 deletions
diff --git a/arch/i386/kernel/cpu/amd.c b/arch/i386/kernel/cpu/amd.c index 4fec702afd7e..6f47eeeb93ea 100644 --- a/arch/i386/kernel/cpu/amd.c +++ b/arch/i386/kernel/cpu/amd.c @@ -280,6 +280,10 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c) if (c->x86 == 0x10 && !force_mwait) clear_bit(X86_FEATURE_MWAIT, c->x86_capability); + + /* K6s reports MCEs but don't actually have all the MSRs */ + if (c->x86 < 6) + clear_bit(X86_FEATURE_MCE, c->x86_capability); } static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 * c, unsigned int size) diff --git a/arch/i386/kernel/cpu/mcheck/k7.c b/arch/i386/kernel/cpu/mcheck/k7.c index f9fa4142551e..eef63e3630c2 100644 --- a/arch/i386/kernel/cpu/mcheck/k7.c +++ b/arch/i386/kernel/cpu/mcheck/k7.c @@ -72,12 +72,12 @@ void amd_mcheck_init(struct cpuinfo_x86 *c) u32 l, h; int i; - machine_check_vector = k7_machine_check; - wmb(); - if (!cpu_has(c, X86_FEATURE_MCE)) return; + machine_check_vector = k7_machine_check; + wmb(); + printk (KERN_INFO "Intel machine check architecture supported.\n"); rdmsr (MSR_IA32_MCG_CAP, l, h); if (l & (1<<8)) /* Control register present ? */ |