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| author |   Guo Ren <ren_guo@c-sky.com> | 2020-01-05 10:52:14 +0800 |
|---|---|---|
| committer |   Paul Walmsley <paul.walmsley@sifive.com> | 2020-01-12 10:12:44 -0800 |
| commit | dc6fcba72f0435b7884f2e92fd634bb9f78a2c60 (patch) | |
| tree | dedfd6d441a9e9f2854a7bccc11bbaccc8580c40 /arch | |
| parent | riscv: move sifive_l2_cache.h to include/soc (diff) | |
| download | linux-dev-dc6fcba72f0435b7884f2e92fd634bb9f78a2c60.tar.xz linux-dev-dc6fcba72f0435b7884f2e92fd634bb9f78a2c60.zip | |
riscv: Fixup obvious bug for fp-regs reset
CSR_MISA is defined in Privileged Architectures' spec: 3.1.1 Machine
ISA Register misa. Every bit:1 indicate a feature, so we should beqz
reset_done when there is no F/D bit in csr_misa register.
Signed-off-by: Guo Ren <ren_guo@c-sky.com>
[paul.walmsley@sifive.com: fix typo in commit message]
Fixes: 9e80635619b51 ("riscv: clear the instruction cache and all registers when booting")
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/riscv/kernel/head.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index 797802c73dee..2227db63f895 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -251,7 +251,7 @@ ENTRY(reset_regs) #ifdef CONFIG_FPU csrr t0, CSR_MISA andi t0, t0, (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D) - bnez t0, .Lreset_regs_done + beqz t0, .Lreset_regs_done li t1, SR_FS csrs CSR_STATUS, t1 |