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| author |   Sean Christopherson <sean.j.christopherson@intel.com> | 2020-01-07 16:12:10 -0800 |
|---|---|---|
| committer |   Paolo Bonzini <pbonzini@redhat.com> | 2020-01-21 14:45:33 +0100 |
| commit | e30a7d623dccdb3f880fbcad980b0cb589a1da45 (patch) | |
| tree | 9e7b362920fc8d26dd0acc223139cc034c18a2db /arch | |
| parent | KVM: nVMX: vmread should not set rflags to specify success in case of #PF (diff) | |
| download | linux-dev-e30a7d623dccdb3f880fbcad980b0cb589a1da45.tar.xz linux-dev-e30a7d623dccdb3f880fbcad980b0cb589a1da45.zip | |
KVM: x86/mmu: Apply max PA check for MMIO sptes to 32-bit KVM
Remove the bogus 64-bit only condition from the check that disables MMIO
spte optimization when the system supports the max PA, i.e. doesn't have
any reserved PA bits. 32-bit KVM always uses PAE paging for the shadow
MMU, and per Intel's SDM:
PAE paging translates 32-bit linear addresses to 52-bit physical
addresses.
The kernel's restrictions on max physical addresses are limits on how
much memory the kernel can reasonably use, not what physical addresses
are supported by hardware.
Fixes: ce88decffd17 ("KVM: MMU: mmio page fault support")
Cc: stable@vger.kernel.org
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/x86/kvm/mmu/mmu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c index 2992ff7b42a7..57e4dbddba72 100644 --- a/arch/x86/kvm/mmu/mmu.c +++ b/arch/x86/kvm/mmu/mmu.c @@ -6193,7 +6193,7 @@ static void kvm_set_mmio_spte_mask(void) * If reserved bit is not supported, clear the present bit to disable * mmio page fault. */ - if (IS_ENABLED(CONFIG_X86_64) && shadow_phys_bits == 52) + if (shadow_phys_bits == 52) mask &= ~1ull; kvm_mmu_set_mmio_spte_mask(mask, mask, ACC_WRITE_MASK | ACC_USER_MASK); |