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| author |   Anup Patel <apatel@ventanamicro.com> | 2022-04-09 09:15:51 +0530 |
|---|---|---|
| committer |   Anup Patel <anup@brainfault.org> | 2022-04-09 09:15:51 +0530 |
| commit | ebdef0de2dbc40e697adaa6b3408130f7a7b8351 (patch) | |
| tree | 829a328b29febec8d7586ff4945a40811c818480 /arch | |
| parent | KVM: selftests: riscv: Set PTE A and D bits in VS-stage page table (diff) | |
| download | linux-dev-ebdef0de2dbc40e697adaa6b3408130f7a7b8351.tar.xz linux-dev-ebdef0de2dbc40e697adaa6b3408130f7a7b8351.zip | |
KVM: selftests: riscv: Fix alignment of the guest_hang() function
The guest_hang() function is used as the default exception handler
for various KVM selftests applications by setting it's address in
the vstvec CSR. The vstvec CSR requires exception handler base address
to be at least 4-byte aligned so this patch fixes alignment of the
guest_hang() function.
Fixes: 3e06cdf10520 ("KVM: selftests: Add initial support for RISC-V
64-bit")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Tested-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'arch')
0 files changed, 0 insertions, 0 deletions