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| author |   Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com> | 2017-08-21 13:17:18 +0200 |
|---|---|---|
| committer |   Tejun Heo <tj@kernel.org> | 2017-10-23 07:09:26 -0700 |
| commit | e8fc8b858cd85de20350bfc72df18306129305b8 (patch) | |
| tree | 8f6b6f3fed870398eb00e0ba342d58997d76e565 /drivers/ata | |
| parent | ata: ceva: Move sata port phy oob settings to device-tree (diff) | |
| download | linux-dev-e8fc8b858cd85de20350bfc72df18306129305b8.tar.xz linux-dev-e8fc8b858cd85de20350bfc72df18306129305b8.zip | |
ata: ceva: Add gen 3 mode support in driver
This patch sets gen 3 mode as default mode in ahci_ceva driver.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
Diffstat (limited to 'drivers/ata')
| -rw-r--r-- | drivers/ata/ahci_ceva.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/ata/ahci_ceva.c b/drivers/ata/ahci_ceva.c index 59de2ca1885c..aa32c8a0f083 100644 --- a/drivers/ata/ahci_ceva.c +++ b/drivers/ata/ahci_ceva.c @@ -60,6 +60,7 @@ #define PORT1_BASE 0x180 /* Port Control Register Bit Definitions */ +#define PORT_SCTL_SPD_GEN3 (0x3 << 4) #define PORT_SCTL_SPD_GEN2 (0x2 << 4) #define PORT_SCTL_SPD_GEN1 (0x1 << 4) #define PORT_SCTL_IPM (0x3 << 8) @@ -136,8 +137,8 @@ static void ahci_ceva_setup(struct ahci_host_priv *hpriv) tmp = PTC_RX_WM_VAL | PTC_RSVD; writel(tmp, mmio + AHCI_VEND_PTC); - /* Default to Gen 2 Speed and Gen 1 if Gen2 is broken */ - tmp = PORT_SCTL_SPD_GEN2 | PORT_SCTL_IPM; + /* Default to Gen 3 Speed and Gen 1 if Gen2 is broken */ + tmp = PORT_SCTL_SPD_GEN3 | PORT_SCTL_IPM; if (cevapriv->flags & CEVA_FLAG_BROKEN_GEN2) tmp = PORT_SCTL_SPD_GEN1 | PORT_SCTL_IPM; writel(tmp, mmio + PORT_SCR_CTL + PORT_BASE + PORT_OFFSET * i); |