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| author |   Eric Anholt <eric@anholt.net> | 2010-08-01 19:23:53 -0700 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2010-08-01 19:34:47 -0700 |
| commit | 2bd34f6ca86b5a5f9b749624f73310820e7a93fd (patch) | |
| tree | 9e42100423e78f400412dfa974a6a13bac94d2c0 /drivers/char/agp/intel-gtt.c | |
| parent | agp/intel: Add actual definitions of the Sandybridge PTE caching bits. (diff) | |
| parent | Linux 2.6.35 (diff) | |
| download | linux-dev-2bd34f6ca86b5a5f9b749624f73310820e7a93fd.tar.xz linux-dev-2bd34f6ca86b5a5f9b749624f73310820e7a93fd.zip | |
Merge remote branch 'origin/master' into drm-intel-next
This resolves the conflict in the EDP code, which has been rather
popular to hack on recently.
Conflicts:
drivers/gpu/drm/i915/intel_dp.c
Diffstat (limited to 'drivers/char/agp/intel-gtt.c')
| -rw-r--r-- | drivers/char/agp/intel-gtt.c | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c index ccd4b1e694d1..0c6d0fe32a21 100644 --- a/drivers/char/agp/intel-gtt.c +++ b/drivers/char/agp/intel-gtt.c @@ -1220,17 +1220,20 @@ static int intel_i915_get_gtt_size(void) /* G33's GTT size defined in gmch_ctrl */ pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); - switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) { - case G33_PGETBL_SIZE_1M: + switch (gmch_ctrl & I830_GMCH_GMS_MASK) { + case I830_GMCH_GMS_STOLEN_512: + size = 512; + break; + case I830_GMCH_GMS_STOLEN_1024: size = 1024; break; - case G33_PGETBL_SIZE_2M: - size = 2048; + case I830_GMCH_GMS_STOLEN_8192: + size = 8*1024; break; default: dev_info(&agp_bridge->dev->dev, "unknown page table size 0x%x, assuming 512KB\n", - (gmch_ctrl & G33_PGETBL_SIZE_MASK)); + (gmch_ctrl & I830_GMCH_GMS_MASK)); size = 512; } } else { |