diff options
| author |   Eric Anholt <eric@anholt.net> | 2010-03-18 12:19:37 -0700 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2010-03-18 16:48:00 -0700 |
| commit | 66f6ff09ff67c45919b336395c4d7d0ed3a97edc (patch) | |
| tree | a559ad7e46eeaca0cb16d3b576e351740d4909df /drivers/char | |
| parent | agp/intel: Respect the GTT size on Sandybridge for scratch page setup. (diff) | |
| download | linux-dev-66f6ff09ff67c45919b336395c4d7d0ed3a97edc.tar.xz linux-dev-66f6ff09ff67c45919b336395c4d7d0ed3a97edc.zip | |
agp/intel: Don't do the chipset flush on Sandybridge.
This CPU should be coherent with graphics in this direction, though
flushing graphics caches are still required. Fixes a system reset on
module load on Sandybridge with 4G+ memory.
Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/char')
| -rw-r--r-- | drivers/char/agp/intel-agp.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c index f499c5e0ca54..b78d5c381efe 100644 --- a/drivers/char/agp/intel-agp.c +++ b/drivers/char/agp/intel-agp.c @@ -97,6 +97,9 @@ EXPORT_SYMBOL(intel_agp_enabled); #define IS_PINEVIEW (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB || \ agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_HB) +#define IS_SNB (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB || \ + agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB) + #define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_EAGLELAKE_HB || \ agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \ agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \ @@ -107,8 +110,7 @@ EXPORT_SYMBOL(intel_agp_enabled); agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB || \ agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB || \ agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB || \ - agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB || \ - agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB) + IS_SNB) extern int agp_memory_reserved; @@ -1204,6 +1206,9 @@ static void intel_i9xx_setup_flush(void) if (intel_private.ifp_resource.start) return; + if (IS_SNB) + return; + /* setup a resource for this object */ intel_private.ifp_resource.name = "Intel Flush Page"; intel_private.ifp_resource.flags = IORESOURCE_MEM; |