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| author |   James Liao <jamesjj.liao@mediatek.com> | 2015-07-10 16:39:34 +0800 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@codeaurora.org> | 2015-07-28 11:58:57 -0700 |
| commit | 75ce0cdb6243d42daca6130e5feb71f536bb136e (patch) | |
| tree | baa25bb3aceeb8638dc98938c02ddd9ae2470ebc /drivers/clk/at91/clk-master.c | |
| parent | clk: mediatek: Fix calculation of PLL rate settings (diff) | |
| download | linux-dev-75ce0cdb6243d42daca6130e5feb71f536bb136e.tar.xz linux-dev-75ce0cdb6243d42daca6130e5feb71f536bb136e.zip | |
clk: mediatek: Add MT8173 MMPLL change rate support
MT8173 MMPLL frequency settings are different from common PLLs.
It needs different post divider settings for some ranges of frequency.
This patch add support for MT8173 MMPLL frequency setting by adding
div-rate table to lookup suitable post divider setting under a
specified frequency.
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/at91/clk-master.c')
0 files changed, 0 insertions, 0 deletions