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| author |   Linus Walleij <linus.walleij@linaro.org> | 2013-09-13 21:45:51 +0200 |
|---|---|---|
| committer |   Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> | 2013-09-22 19:52:46 +0200 |
| commit | eb6b036dde364c528807f53ee8c8e5c9b0e46c34 (patch) | |
| tree | f4bb094bd000264f4762cffb884061684aeeaf0e /drivers/clk/clk-nomadik.c | |
| parent | Merge tag 'tegra-for-3.13-deps-for-arm-init-time-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into clk-of-init-v2_for-3.13 (diff) | |
| download | linux-dev-eb6b036dde364c528807f53ee8c8e5c9b0e46c34.tar.xz linux-dev-eb6b036dde364c528807f53ee8c8e5c9b0e46c34.zip | |
clk: nomadik: set all timers to use 2.4 MHz TIMCLK
This fixes a regression for the Nomadik on the main system
timers.
The Nomadik seemed a bit slow and its heartbeat wasn't looking
healthy. And it was not strange, because it has been connected
to the 32768 Hz clock at boot, while being told by the clock driver
that it was 2.4MHz. Actually connect the TIMCLK to 2.4MHz by
default as this is what we want for nice scheduling, clocksource
and clock event.
Cc: stable@vger.kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/clk/clk-nomadik.c')
| -rw-r--r-- | drivers/clk/clk-nomadik.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/drivers/clk/clk-nomadik.c b/drivers/clk/clk-nomadik.c index 51410c2ac2cb..4d978a3c88f7 100644 --- a/drivers/clk/clk-nomadik.c +++ b/drivers/clk/clk-nomadik.c @@ -27,6 +27,14 @@ */ #define SRC_CR 0x00U +#define SRC_CR_T0_ENSEL BIT(15) +#define SRC_CR_T1_ENSEL BIT(17) +#define SRC_CR_T2_ENSEL BIT(19) +#define SRC_CR_T3_ENSEL BIT(21) +#define SRC_CR_T4_ENSEL BIT(23) +#define SRC_CR_T5_ENSEL BIT(25) +#define SRC_CR_T6_ENSEL BIT(27) +#define SRC_CR_T7_ENSEL BIT(29) #define SRC_XTALCR 0x0CU #define SRC_XTALCR_XTALTIMEN BIT(20) #define SRC_XTALCR_SXTALDIS BIT(19) @@ -543,6 +551,19 @@ void __init nomadik_clk_init(void) __func__, np->name); return; } + + /* Set all timers to use the 2.4 MHz TIMCLK */ + val = readl(src_base + SRC_CR); + val |= SRC_CR_T0_ENSEL; + val |= SRC_CR_T1_ENSEL; + val |= SRC_CR_T2_ENSEL; + val |= SRC_CR_T3_ENSEL; + val |= SRC_CR_T4_ENSEL; + val |= SRC_CR_T5_ENSEL; + val |= SRC_CR_T6_ENSEL; + val |= SRC_CR_T7_ENSEL; + writel(val, src_base + SRC_CR); + val = readl(src_base + SRC_XTALCR); pr_info("SXTALO is %s\n", (val & SRC_XTALCR_SXTALDIS) ? "disabled" : "enabled"); |