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authorTony Prisk <linux@prisktech.co.nz>2013-05-13 20:21:00 +1200
committerMike Turquette <mturquette@linaro.org>2013-05-29 14:47:17 -0700
commit65f2c58f0f44403aa64eccc14f3a0a74d721fe7e (patch)
tree37b8ac6bb648af43d283538608aa7b7a26738bc5 /drivers/clk/clk-vt8500.c
parentclk: vt8500: Add support for clocks on the WM8850 SoCs (diff)
downloadlinux-dev-65f2c58f0f44403aa64eccc14f3a0a74d721fe7e.tar.xz
linux-dev-65f2c58f0f44403aa64eccc14f3a0a74d721fe7e.zip
clk: vt8500: Remove unnecessary divisor adjustment in vtwm_dclk_set_rate()
The divisor adjustment code to ensure that a divisor is not rounded down, thereby giving a rate higher than requested, is unnecessary and in some instances results in the actual rate being much lower than requested due to rounding errors. The test is already performed in vtwm_dclk_round_rate(), which is always called when clk_set_rate is called. Due to rounding errors in the line: divisor = parent_rate / rate (clk-vt8500.c:160) we will sometimes end up adjusting the divisor twice - first in round_rate and then again in set_rate. This patch removes the test/adjustment in vtwm_dclk_set_rate. Signed-off-by: Tony Prisk <linux@prisktech.co.nz> Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk/clk-vt8500.c')
-rw-r--r--drivers/clk/clk-vt8500.c4
1 files changed, 0 insertions, 4 deletions
diff --git a/drivers/clk/clk-vt8500.c b/drivers/clk/clk-vt8500.c
index 6d5b6e901b96..d8fd085719bf 100644
--- a/drivers/clk/clk-vt8500.c
+++ b/drivers/clk/clk-vt8500.c
@@ -157,10 +157,6 @@ static int vt8500_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
divisor = parent_rate / rate;
- /* If prate / rate would be decimal, incr the divisor */
- if (rate * divisor < parent_rate)
- divisor++;
-
if (divisor == cdev->div_mask + 1)
divisor = 0;