diff options
| author |   Peng Fan <peng.fan@nxp.com> | 2019-05-31 15:56:38 +0800 |
|---|---|---|
| committer |   Shawn Guo <shawnguo@kernel.org> | 2019-06-07 08:18:10 +0800 |
| commit | 5b933e28d8b1fbdc7fbac4bfc569f3b152c3dd59 (patch) | |
| tree | 9625c5456054f730633aab449ede8cb7e1b69122 /drivers/clk/imx/clk-imx8mm.c | |
| parent | clk: imx: keep the mmdc p1 ipg clock always on on 6sx/ul/ull/sll (diff) | |
| download | linux-dev-5b933e28d8b1fbdc7fbac4bfc569f3b152c3dd59.tar.xz linux-dev-5b933e28d8b1fbdc7fbac4bfc569f3b152c3dd59.zip | |
clk: imx: imx8mm: correct audio_pll2_clk to audio_pll2_out
There is no audio_pll2_clk registered, it should be audio_pll2_out.
Cc: <stable@vger.kernel.org>
Fixes: ba5625c3e272 ("clk: imx: Add clock driver support for imx8mm")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'drivers/clk/imx/clk-imx8mm.c')
| -rw-r--r-- | drivers/clk/imx/clk-imx8mm.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index 66a1cb661006..3a873e0e278f 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -328,7 +328,7 @@ static const char *imx8mm_dsi_dbi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll1_out", }; static const char *imx8mm_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m", - "sys_pll3_out", "sys_pll1_266m", "audio_pll2_clk", "sys_pll1_100m", }; + "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", }; static const char *imx8mm_csi1_core_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll1_out", }; @@ -364,11 +364,11 @@ static const char *imx8mm_pdm_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_ "sys_pll2_1000m", "sys_pll3_out", "clk_ext3", "audio_pll2_out", }; static const char *imx8mm_vpu_h1_sels[] = {"osc_24m", "vpu_pll_out", "sys_pll1_800m", "sys_pll2_1000m", - "audio_pll2_clk", "sys_pll2_125m", "sys_pll3_clk", "audio_pll1_out", }; + "audio_pll2_out", "sys_pll2_125m", "sys_pll3_clk", "audio_pll1_out", }; static const char *imx8mm_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", }; -static const char *imx8mm_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "osc_27m", "sys_pll1_200m", "audio_pll2_clk", +static const char *imx8mm_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "osc_27m", "sys_pll1_200m", "audio_pll2_out", "vpu_pll", "sys_pll1_80m", }; static struct clk *clks[IMX8MM_CLK_END]; |