diff options
| author |   Leonard Crestez <leonard.crestez@nxp.com> | 2019-11-22 23:45:01 +0200 |
|---|---|---|
| committer |   Shawn Guo <shawnguo@kernel.org> | 2019-12-09 09:15:26 +0800 |
| commit | e18f64712e9ef22054da1babe425d2a5892edcd4 (patch) | |
| tree | 7631e7979f5942135e50dec9fc459c0897285011 /drivers/clk/imx/clk-imx8mn.c | |
| parent | clk: imx8m: Set CLK_GET_RATE_NOCACHE on dram clocks (diff) | |
| download | linux-dev-e18f64712e9ef22054da1babe425d2a5892edcd4.tar.xz linux-dev-e18f64712e9ef22054da1babe425d2a5892edcd4.zip | |
clk: imx: Mark dram pll on 8mm and 8mn with CLK_GET_RATE_NOCACHE
DRAM frequency switches are executed in firmware and can change the
configuration of the DRAM PLL outside linux. Mark these CLKs with
CLK_GET_RATE_NOCACHE so we always read back the PLL config registers and
recalculate rates.
In current DRAM frequency tables on 8mm/8mn only the maximum frequency
uses the PLL so it's always configured in the same way. However reading
back the PLL configuration is the correct behavior and allows additional
setpoints in the future.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'drivers/clk/imx/clk-imx8mn.c')
| -rw-r--r-- | drivers/clk/imx/clk-imx8mn.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index de905e278b80..4749beab9fc8 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -325,7 +325,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) clks[IMX8MN_AUDIO_PLL1] = imx_clk_pll14xx("audio_pll1", "audio_pll1_ref_sel", base, &imx_1443x_pll); clks[IMX8MN_AUDIO_PLL2] = imx_clk_pll14xx("audio_pll2", "audio_pll2_ref_sel", base + 0x14, &imx_1443x_pll); clks[IMX8MN_VIDEO_PLL1] = imx_clk_pll14xx("video_pll1", "video_pll1_ref_sel", base + 0x28, &imx_1443x_pll); - clks[IMX8MN_DRAM_PLL] = imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx_1443x_pll); + clks[IMX8MN_DRAM_PLL] = imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx_1443x_dram_pll); clks[IMX8MN_GPU_PLL] = imx_clk_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, &imx_1416x_pll); clks[IMX8MN_VPU_PLL] = imx_clk_pll14xx("vpu_pll", "vpu_pll_ref_sel", base + 0x74, &imx_1416x_pll); clks[IMX8MN_ARM_PLL] = imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, &imx_1416x_pll); |