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| author |   Paul Cercueil <paul@crapouillou.net> | 2018-06-27 14:14:58 +0200 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2018-07-06 11:47:27 -0700 |
| commit | 574f4e80d59e5c669c0729718525df8bac5e4d78 (patch) | |
| tree | 05f31b76958f5f13727b0ec57738007478e3f4bf /drivers/clk/ingenic/jz4740-cgu.c | |
| parent | Linux 4.18-rc1 (diff) | |
| download | linux-dev-574f4e80d59e5c669c0729718525df8bac5e4d78.tar.xz linux-dev-574f4e80d59e5c669c0729718525df8bac5e4d78.zip | |
clk: ingenic: Fix incorrect data for the i2s clock
The register field for configuring the divider for the i2s clock
occupies the bits [8-0], which means 9 bits and not 8.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/ingenic/jz4740-cgu.c')
| -rw-r--r-- | drivers/clk/ingenic/jz4740-cgu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/ingenic/jz4740-cgu.c b/drivers/clk/ingenic/jz4740-cgu.c index 32fcc75f6f77..bc073dd4470d 100644 --- a/drivers/clk/ingenic/jz4740-cgu.c +++ b/drivers/clk/ingenic/jz4740-cgu.c @@ -134,7 +134,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = { "i2s", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 }, .mux = { CGU_REG_CPCCR, 31, 1 }, - .div = { CGU_REG_I2SCDR, 0, 1, 8, -1, -1, -1 }, + .div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 }, .gate = { CGU_REG_CLKGR, 6 }, }, |