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| author |   Aidan MacDonald <aidanmacdonald.0x0@gmail.com> | 2022-04-28 17:44:53 +0100 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2022-05-18 13:56:22 -0700 |
| commit | ca54d06fcacfdeb0b07acb4c6469a96fb02a9b44 (patch) | |
| tree | 096e8d883fa8a0e6d9defd626fa28ff720d78181 /drivers/clk/ingenic/jz4760-cgu.c | |
| parent | clk: ingenic: Allow specifying common clock flags (diff) | |
| download | linux-dev-ca54d06fcacfdeb0b07acb4c6469a96fb02a9b44.tar.xz linux-dev-ca54d06fcacfdeb0b07acb4c6469a96fb02a9b44.zip | |
clk: ingenic: Mark critical clocks in Ingenic SoCs
Consider CPU, L2 cache, and memory clocks as critical to prevent
them -- and the parent clocks -- from being automatically gated,
since nothing calls clk_get() on these clocks.
Gating the CPU clock hangs the processor, and gating memory makes
external DRAM inaccessible. Normal kernel code can't hope to deal
with either situation so those clocks have to be critical.
The L2 cache is required only if caches are running, and could be
gated if the kernel takes care to flush and disable caches before
gating the clock. There's no mechanism to do this, and probably no
reason to do it, so it's simpler to mark the L2 cache as critical.
Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20220428164454.17908-3-aidanmacdonald.0x0@gmail.com
Tested-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> # On X1000 and X1830
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/ingenic/jz4760-cgu.c')
| -rw-r--r-- | drivers/clk/ingenic/jz4760-cgu.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/clk/ingenic/jz4760-cgu.c b/drivers/clk/ingenic/jz4760-cgu.c index 8fdd383560fb..ecd395ac8a28 100644 --- a/drivers/clk/ingenic/jz4760-cgu.c +++ b/drivers/clk/ingenic/jz4760-cgu.c @@ -143,6 +143,11 @@ static const struct ingenic_cgu_clk_info jz4760_cgu_clocks[] = { [JZ4760_CLK_CCLK] = { "cclk", CGU_CLK_DIV, + /* + * Disabling the CPU clock or any parent clocks will hang the + * system; mark it critical. + */ + .flags = CLK_IS_CRITICAL, .parents = { JZ4760_CLK_PLL0, }, .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0, @@ -175,6 +180,11 @@ static const struct ingenic_cgu_clk_info jz4760_cgu_clocks[] = { }, [JZ4760_CLK_MCLK] = { "mclk", CGU_CLK_DIV, + /* + * Disabling MCLK or its parents will render DRAM + * inaccessible; mark it critical. + */ + .flags = CLK_IS_CRITICAL, .parents = { JZ4760_CLK_PLL0, }, .div = { CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0, |