diff options
| author |   Paul Cercueil <paul@crapouillou.net> | 2019-06-11 20:07:54 +0200 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2019-06-25 15:43:15 -0700 |
| commit | 2ee93e3c953b7263c21ce61e7c42e33d0539bef9 (patch) | |
| tree | c6dd6351f5350bb9724f2fcc6f13a1b0335b5d22 /drivers/clk/ingenic/jz4770-cgu.c | |
| parent | clk: ingenic: Add missing header in cgu.h (diff) | |
| download | linux-dev-2ee93e3c953b7263c21ce61e7c42e33d0539bef9.tar.xz linux-dev-2ee93e3c953b7263c21ce61e7c42e33d0539bef9.zip | |
clk: ingenic: Handle setting the Low-Power Mode bit
The Low-Power Mode, when enabled, will make the "wait" MIPS instruction
suspend the system.
This is not really clock-related, but this bit happens to be in the
register set of the CGU.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/ingenic/jz4770-cgu.c')
| -rw-r--r-- | drivers/clk/ingenic/jz4770-cgu.c | 33 |
1 files changed, 2 insertions, 31 deletions
diff --git a/drivers/clk/ingenic/jz4770-cgu.c b/drivers/clk/ingenic/jz4770-cgu.c index 2a29da442a8e..eebc1bea3841 100644 --- a/drivers/clk/ingenic/jz4770-cgu.c +++ b/drivers/clk/ingenic/jz4770-cgu.c @@ -9,9 +9,9 @@ #include <linux/delay.h> #include <linux/io.h> #include <linux/of.h> -#include <linux/syscore_ops.h> #include <dt-bindings/clock/jz4770-cgu.h> #include "cgu.h" +#include "pm.h" /* * CPM registers offset address definition @@ -38,9 +38,6 @@ #define CGU_REG_MSC2CDR 0xA8 #define CGU_REG_BCHCDR 0xAC -/* bits within the LCR register */ -#define LCR_LPM BIT(0) /* Low Power Mode */ - /* bits within the OPCR register */ #define OPCR_SPENDH BIT(5) /* UHC PHY suspend */ @@ -429,30 +426,6 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = { }, }; -#if IS_ENABLED(CONFIG_PM_SLEEP) -static int jz4770_cgu_pm_suspend(void) -{ - u32 val; - - val = readl(cgu->base + CGU_REG_LCR); - writel(val | LCR_LPM, cgu->base + CGU_REG_LCR); - return 0; -} - -static void jz4770_cgu_pm_resume(void) -{ - u32 val; - - val = readl(cgu->base + CGU_REG_LCR); - writel(val & ~LCR_LPM, cgu->base + CGU_REG_LCR); -} - -static struct syscore_ops jz4770_cgu_pm_ops = { - .suspend = jz4770_cgu_pm_suspend, - .resume = jz4770_cgu_pm_resume, -}; -#endif /* CONFIG_PM_SLEEP */ - static void __init jz4770_cgu_init(struct device_node *np) { int retval; @@ -466,9 +439,7 @@ static void __init jz4770_cgu_init(struct device_node *np) if (retval) pr_err("%s: failed to register CGU Clocks\n", __func__); -#if IS_ENABLED(CONFIG_PM_SLEEP) - register_syscore_ops(&jz4770_cgu_pm_ops); -#endif + ingenic_cgu_register_syscore_ops(cgu); } /* We only probe via devicetree, no need for a platform driver */ |