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authorChun-Jie Chen <chun-jie.chen@mediatek.com>2021-07-26 18:57:07 +0800
committerStephen Boyd <sboyd@kernel.org>2021-07-27 10:53:07 -0700
commit710573dee31b4ca34abeb384c6e3db499c0af65f (patch)
treeafaa2cfd9b52f1836f5b2bb1cfc1409f80951bdb /drivers/clk/mediatek/clk-mux.c
parentclk: mediatek: Add mtk_clk_simple_probe() to simplify clock providers (diff)
downloadlinux-dev-710573dee31b4ca34abeb384c6e3db499c0af65f.tar.xz
linux-dev-710573dee31b4ca34abeb384c6e3db499c0af65f.zip
clk: mediatek: Add MT8192 basic clocks support
Add MT8192 basic clock providers, include topckgen, apmixedsys, infracfg and pericfg. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Link: https://lore.kernel.org/r/20210726105719.15793-10-chun-jie.chen@mediatek.com Reviewed-by: Ikjoon Jang <ikjn@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/mediatek/clk-mux.c')
-rw-r--r--drivers/clk/mediatek/clk-mux.c9
1 files changed, 7 insertions, 2 deletions
diff --git a/drivers/clk/mediatek/clk-mux.c b/drivers/clk/mediatek/clk-mux.c
index e97d58db28cc..855b0a1f7eb9 100644
--- a/drivers/clk/mediatek/clk-mux.c
+++ b/drivers/clk/mediatek/clk-mux.c
@@ -116,7 +116,12 @@ static int mtk_clk_mux_set_parent_setclr_lock(struct clk_hw *hw, u8 index)
return 0;
}
-static const struct clk_ops mtk_mux_ops = {
+const struct clk_ops mtk_mux_clr_set_upd_ops = {
+ .get_parent = mtk_clk_mux_get_parent,
+ .set_parent = mtk_clk_mux_set_parent_setclr_lock,
+};
+
+const struct clk_ops mtk_mux_gate_clr_set_upd_ops = {
.enable = mtk_clk_mux_enable_setclr,
.disable = mtk_clk_mux_disable_setclr,
.is_enabled = mtk_clk_mux_is_enabled,
@@ -140,7 +145,7 @@ static struct clk *mtk_clk_register_mux(const struct mtk_mux *mux,
init.flags = mux->flags | CLK_SET_RATE_PARENT;
init.parent_names = mux->parent_names;
init.num_parents = mux->num_parents;
- init.ops = &mtk_mux_ops;
+ init.ops = mux->ops;
clk_mux->regmap = regmap;
clk_mux->data = mux;