diff options
| author |   Shunli Wang <shunli.wang@mediatek.com> | 2016-11-04 15:43:05 +0800 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@codeaurora.org> | 2016-11-08 15:59:49 -0800 |
| commit | e9862118272aa528e35e54ef9f1e35c217870fd7 (patch) | |
| tree | 8dc89a1e94dfef635dab7ac98d423cda5247627a /drivers/clk/mediatek/clk-pll.c | |
| parent | clk: pxa mark dummy helper as 'inline' (diff) | |
| download | linux-dev-e9862118272aa528e35e54ef9f1e35c217870fd7.tar.xz linux-dev-e9862118272aa528e35e54ef9f1e35c217870fd7.zip | |
clk: mediatek: Add MT2701 clock support
Add MT2701 clock support, include topckgen, apmixedsys,
infracfg, pericfg and subsystem clocks.
Signed-off-by: Shunli Wang <shunli.wang@mediatek.com>
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Signed-off-by: Erin Lo <erin.lo@mediatek.com>
Tested-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/mediatek/clk-pll.c')
| -rw-r--r-- | drivers/clk/mediatek/clk-pll.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c index 0c2deac17ce9..a409142e9346 100644 --- a/drivers/clk/mediatek/clk-pll.c +++ b/drivers/clk/mediatek/clk-pll.c @@ -301,6 +301,7 @@ static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data, pll->data = data; init.name = data->name; + init.flags = (data->flags & PLL_AO) ? CLK_IS_CRITICAL : 0; init.ops = &mtk_pll_ops; init.parent_names = &parent_name; init.num_parents = 1; |