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| author |   Jerome Brunet <jbrunet@baylibre.com> | 2018-02-12 15:58:31 +0100 |
|---|---|---|
| committer |   Neil Armstrong <narmstrong@baylibre.com> | 2018-03-13 10:03:58 +0100 |
| commit | 7b174c5ebe46c739b0802d0781a32788f5259d2c (patch) | |
| tree | e106f099794faa51c2593ac0c31fd047e794868e /drivers/clk/meson/axg.c | |
| parent | clk: meson: only one loop index is necessary in probe (diff) | |
| download | linux-dev-7b174c5ebe46c739b0802d0781a32788f5259d2c.tar.xz linux-dev-7b174c5ebe46c739b0802d0781a32788f5259d2c.zip | |
clk: meson: remove obsolete comments
Over time things changes in CCF and issues have been fixed in meson
controllers.
Now, clk81 is decently modeled by read-only PLLs, a mux, a divider
and a gate. We can remove the FIXME comments related to clk81.
Also remove the comment about devm_clk_hw_register, as there is
apparently nothing wrong with it.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Diffstat (limited to 'drivers/clk/meson/axg.c')
| -rw-r--r-- | drivers/clk/meson/axg.c | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index 3bb77b4f1e8d..bc5c29f13282 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -411,11 +411,6 @@ static struct meson_clk_mpll axg_mpll3 = { }, }; -/* - * FIXME The legacy composite clocks (e.g. clk81) are both PLL post-dividers - * and should be modeled with their respective PLLs via the forthcoming - * coordinated clock rates feature - */ static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 }; static const char * const clk81_parent_names[] = { "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4", |