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| author |   Jerome Brunet <jbrunet@baylibre.com> | 2018-08-01 16:00:50 +0200 |
|---|---|---|
| committer | Jerome Brunet <jbrunet@baylibre.com> | 2018-09-26 12:00:28 +0200 |
| commit | e40c7e3cda07099a92ea68d022f3304c14f9659f (patch) | |
| tree | 1d1405f53c13cd285e30953d8880a59a1bc5cae7 /drivers/clk/meson/axg.c | |
| parent | Linux 4.19-rc1 (diff) | |
| download | linux-dev-e40c7e3cda07099a92ea68d022f3304c14f9659f.tar.xz linux-dev-e40c7e3cda07099a92ea68d022f3304c14f9659f.zip | |
clk: meson: clk-pll: add enable bit
Add the enable the bit of the pll clocks.
These pll clocks may be disabled but we can't model this as an external
gate since the pll needs to lock when enabled.
Adding this bit allows to drop the poke of the first register of PLL.
This will be useful to model the different components of the pll using
generic clocks elements
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'drivers/clk/meson/axg.c')
| -rw-r--r-- | drivers/clk/meson/axg.c | 28 |
1 files changed, 25 insertions, 3 deletions
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index 00ce62ad6416..6d8976554656 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -24,6 +24,11 @@ static DEFINE_SPINLOCK(meson_clk_lock); static struct clk_regmap axg_fixed_pll = { .data = &(struct meson_clk_pll_data){ + .en = { + .reg_off = HHI_MPLL_CNTL, + .shift = 30, + .width = 1, + }, .m = { .reg_off = HHI_MPLL_CNTL, .shift = 0, @@ -65,6 +70,11 @@ static struct clk_regmap axg_fixed_pll = { static struct clk_regmap axg_sys_pll = { .data = &(struct meson_clk_pll_data){ + .en = { + .reg_off = HHI_SYS_PLL_CNTL, + .shift = 30, + .width = 1, + }, .m = { .reg_off = HHI_SYS_PLL_CNTL, .shift = 0, @@ -197,11 +207,15 @@ static const struct reg_sequence axg_gp0_init_regs[] = { { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 }, { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d }, { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 }, - { .reg = HHI_GP0_PLL_CNTL, .def = 0x40010250 }, }; static struct clk_regmap axg_gp0_pll = { .data = &(struct meson_clk_pll_data){ + .en = { + .reg_off = HHI_GP0_PLL_CNTL, + .shift = 30, + .width = 1, + }, .m = { .reg_off = HHI_GP0_PLL_CNTL, .shift = 0, @@ -250,11 +264,15 @@ static const struct reg_sequence axg_hifi_init_regs[] = { { .reg = HHI_HIFI_PLL_CNTL3, .def = 0x0a6a3a88 }, { .reg = HHI_HIFI_PLL_CNTL4, .def = 0xc000004d }, { .reg = HHI_HIFI_PLL_CNTL5, .def = 0x00058000 }, - { .reg = HHI_HIFI_PLL_CNTL, .def = 0x40010250 }, }; static struct clk_regmap axg_hifi_pll = { .data = &(struct meson_clk_pll_data){ + .en = { + .reg_off = HHI_HIFI_PLL_CNTL, + .shift = 30, + .width = 1, + }, .m = { .reg_off = HHI_HIFI_PLL_CNTL, .shift = 0, @@ -637,7 +655,6 @@ static const struct pll_rate_table axg_pcie_pll_rate_table[] = { }; static const struct reg_sequence axg_pcie_init_regs[] = { - { .reg = HHI_PCIE_PLL_CNTL, .def = 0x400106c8 }, { .reg = HHI_PCIE_PLL_CNTL1, .def = 0x0084a2aa }, { .reg = HHI_PCIE_PLL_CNTL2, .def = 0xb75020be }, { .reg = HHI_PCIE_PLL_CNTL3, .def = 0x0a47488e }, @@ -648,6 +665,11 @@ static const struct reg_sequence axg_pcie_init_regs[] = { static struct clk_regmap axg_pcie_pll = { .data = &(struct meson_clk_pll_data){ + .en = { + .reg_off = HHI_PCIE_PLL_CNTL, + .shift = 30, + .width = 1, + }, .m = { .reg_off = HHI_PCIE_PLL_CNTL, .shift = 0, |