diff options
| author |   Jerome Brunet <jbrunet@baylibre.com> | 2018-02-12 15:58:43 +0100 |
|---|---|---|
| committer |   Neil Armstrong <narmstrong@baylibre.com> | 2018-03-13 10:04:03 +0100 |
| commit | d610b54f77002bbddca54c10d9488c2faa7ff102 (patch) | |
| tree | a991e55607dc05c8f35690122bb66dad30ae55ec /drivers/clk/meson/axg.h | |
| parent | clk: meson: migrate plls clocks to clk_regmap (diff) | |
| download | linux-dev-d610b54f77002bbddca54c10d9488c2faa7ff102.tar.xz linux-dev-d610b54f77002bbddca54c10d9488c2faa7ff102.zip | |
clk: meson: split divider and gate part of mpll
The mpll clock is a kind of fractional divider which can gate.
When the RW operation have been added, enable/disable ops have been
mistakenly inserted in this driver. These ops are essentially a
poor copy/paste of the generic gate ops.
This change removes the gate ops from the mpll driver and inserts a
generic gate clock on each mpll divider, simplifying the mpll
driver and reducing code duplication.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Diffstat (limited to 'drivers/clk/meson/axg.h')
| -rw-r--r-- | drivers/clk/meson/axg.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/clk/meson/axg.h b/drivers/clk/meson/axg.h index ce0bafdb6b28..4c1502a8b8c9 100644 --- a/drivers/clk/meson/axg.h +++ b/drivers/clk/meson/axg.h @@ -117,8 +117,12 @@ #define CLKID_SD_EMMC_B_CLK0_DIV 62 #define CLKID_SD_EMMC_C_CLK0_SEL 63 #define CLKID_SD_EMMC_C_CLK0_DIV 64 +#define CLKID_MPLL0_DIV 65 +#define CLKID_MPLL1_DIV 66 +#define CLKID_MPLL2_DIV 67 +#define CLKID_MPLL3_DIV 68 -#define NR_CLKS 65 +#define NR_CLKS 69 /* include the CLKIDs that have been made part of the DT binding */ #include <dt-bindings/clock/axg-clkc.h> |