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| author |   Jian Hu <jian.hu@amlogic.com> | 2019-02-01 15:53:44 +0100 |
|---|---|---|
| committer |   Neil Armstrong <narmstrong@baylibre.com> | 2019-02-04 09:52:11 +0100 |
| commit | 085a4ea93d5491b9e5274272b528a1fccf9b2546 (patch) | |
| tree | 70e33bdaef55ddd3763a0f0f4b0f5cde9f1fd4a7 /drivers/clk/meson/clk-regmap.h | |
| parent | dt-bindings: clk: meson: add g12a periph clock controller bindings (diff) | |
| download | linux-dev-085a4ea93d5491b9e5274272b528a1fccf9b2546.tar.xz linux-dev-085a4ea93d5491b9e5274272b528a1fccf9b2546.zip | |
clk: meson: g12a: add peripheral clock controller
Add the peripheral clock controller found in the g12a SoC family
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20190201145345.6795-4-jbrunet@baylibre.com
Diffstat (limited to 'drivers/clk/meson/clk-regmap.h')
| -rw-r--r-- | drivers/clk/meson/clk-regmap.h | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/drivers/clk/meson/clk-regmap.h b/drivers/clk/meson/clk-regmap.h index b7a085bbf072..1dd0abe3ba91 100644 --- a/drivers/clk/meson/clk-regmap.h +++ b/drivers/clk/meson/clk-regmap.h @@ -111,7 +111,7 @@ clk_get_regmap_mux_data(struct clk_regmap *clk) extern const struct clk_ops clk_regmap_mux_ops; extern const struct clk_ops clk_regmap_mux_ro_ops; -#define MESON_GATE(_name, _reg, _bit) \ +#define __MESON_GATE(_name, _reg, _bit, _ops) \ struct clk_regmap _name = { \ .data = &(struct clk_regmap_gate_data){ \ .offset = (_reg), \ @@ -119,11 +119,16 @@ struct clk_regmap _name = { \ }, \ .hw.init = &(struct clk_init_data) { \ .name = #_name, \ - .ops = &clk_regmap_gate_ops, \ + .ops = _ops, \ .parent_names = (const char *[]){ "clk81" }, \ .num_parents = 1, \ .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \ }, \ } +#define MESON_GATE(_name, _reg, _bit) \ + __MESON_GATE(_name, _reg, _bit, &clk_regmap_gate_ops) + +#define MESON_GATE_RO(_name, _reg, _bit) \ + __MESON_GATE(_name, _reg, _bit, &clk_regmap_gate_ro_ops) #endif /* __CLK_REGMAP_H */ |