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| author |   Jerome Brunet <jbrunet@baylibre.com> | 2019-05-13 14:31:11 +0200 |
|---|---|---|
| committer | Jerome Brunet <jbrunet@baylibre.com> | 2019-05-20 12:18:55 +0200 |
| commit | dc4e62d373f881cbf51513296a6db7806516a01a (patch) | |
| tree | 188605959275fc3943f12417ec03e53506d79c18 /drivers/clk/meson | |
| parent | clk: meson: gxbb: no spread spectrum on mpll0 (diff) | |
| download | linux-dev-dc4e62d373f881cbf51513296a6db7806516a01a.tar.xz linux-dev-dc4e62d373f881cbf51513296a6db7806516a01a.zip | |
clk: meson: axg: spread spectrum is on mpll2
After testing, it appears that the SSEN bit controls the spread
spectrum function on MPLL2, not MPLL0.
Fixes: 78b4af312f91 ("clk: meson-axg: add clock controller drivers")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'drivers/clk/meson')
| -rw-r--r-- | drivers/clk/meson/axg.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index 7a8ef80e5f2c..3ddd0efc9ee0 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -469,11 +469,6 @@ static struct clk_regmap axg_mpll0_div = { .shift = 16, .width = 9, }, - .ssen = { - .reg_off = HHI_MPLL_CNTL, - .shift = 25, - .width = 1, - }, .misc = { .reg_off = HHI_PLL_TOP_MISC, .shift = 0, @@ -568,6 +563,11 @@ static struct clk_regmap axg_mpll2_div = { .shift = 16, .width = 9, }, + .ssen = { + .reg_off = HHI_MPLL_CNTL, + .shift = 25, + .width = 1, + }, .misc = { .reg_off = HHI_PLL_TOP_MISC, .shift = 2, |