diff options
| author |   Terry Zhou <bjzhou@marvell.com> | 2020-11-06 11:00:39 +0100 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2020-12-19 15:51:18 -0800 |
| commit | 6f37689cf6b38fff96de52e7f0d3e78f22803ba0 (patch) | |
| tree | 0242978f543481ee98806961a1ef2ed70d678225 /drivers/clk/mvebu | |
| parent | Linux 5.10-rc1 (diff) | |
| download | linux-dev-6f37689cf6b38fff96de52e7f0d3e78f22803ba0.tar.xz linux-dev-6f37689cf6b38fff96de52e7f0d3e78f22803ba0.zip | |
clk: mvebu: a3700: fix the XTAL MODE pin to MPP1_9
There is an error in the current code that the XTAL MODE
pin was set to NB MPP1_31 which should be NB MPP1_9.
The latch register of NB MPP1_9 has different offset of 0x8.
Signed-off-by: Terry Zhou <bjzhou@marvell.com>
[pali: Fix pin name in commit message]
Signed-off-by: Pali Rohár <pali@kernel.org>
Fixes: 7ea8250406a6 ("clk: mvebu: Add the xtal clock for Armada 3700 SoC")
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20201106100039.11385-1-pali@kernel.org
Reviewed-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/mvebu')
| -rw-r--r-- | drivers/clk/mvebu/armada-37xx-xtal.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/mvebu/armada-37xx-xtal.c b/drivers/clk/mvebu/armada-37xx-xtal.c index e9e306d4e9af..41271351cf1f 100644 --- a/drivers/clk/mvebu/armada-37xx-xtal.c +++ b/drivers/clk/mvebu/armada-37xx-xtal.c @@ -13,8 +13,8 @@ #include <linux/platform_device.h> #include <linux/regmap.h> -#define NB_GPIO1_LATCH 0xC -#define XTAL_MODE BIT(31) +#define NB_GPIO1_LATCH 0x8 +#define XTAL_MODE BIT(9) static int armada_3700_xtal_clock_probe(struct platform_device *pdev) { |