diff options
| author |   Arnd Bergmann <arnd@arndb.de> | 2019-09-18 17:42:52 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2022-05-07 22:55:49 +0200 |
| commit | fd13f8117f7a2d4054bf420ec1428e918a24a480 (patch) | |
| tree | 99c55a437057e8277373a261f769577c6b27cbe3 /drivers/clk/pxa/clk-pxa3xx.c | |
| parent | cpufreq: pxa3: move clk register access to clk driver (diff) | |
| download | linux-dev-fd13f8117f7a2d4054bf420ec1428e918a24a480.tar.xz linux-dev-fd13f8117f7a2d4054bf420ec1428e918a24a480.zip | |
ARM: pxa: move smemc register access from clk to platform
The get_sdram_rows() and get_memclkdiv() helpers need smemc
register that are separate from the clk registers, move
them out of the clk driver, and use an extern declaration
instead.
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: linux-clk@vger.kernel.org
Link: https://lore.kernel.org/lkml/87pnielzo4.fsf@belgarion.home/
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'drivers/clk/pxa/clk-pxa3xx.c')
| -rw-r--r-- | drivers/clk/pxa/clk-pxa3xx.c | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/drivers/clk/pxa/clk-pxa3xx.c b/drivers/clk/pxa/clk-pxa3xx.c index 60a0db4f3790..08594fc899e2 100644 --- a/drivers/clk/pxa/clk-pxa3xx.c +++ b/drivers/clk/pxa/clk-pxa3xx.c @@ -15,7 +15,7 @@ #include <linux/clkdev.h> #include <linux/of.h> #include <linux/soc/pxa/cpu.h> -#include <mach/smemc.h> +#include <linux/soc/pxa/smemc.h> #include <linux/clk/pxa.h> #include <mach/pxa3xx-regs.h> @@ -41,8 +41,6 @@ static unsigned char hss_mult[4] = { 8, 12, 16, 24 }; /* crystal frequency to static memory controller multiplier (SMCFS) */ static unsigned int smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, }; -static unsigned int df_clkdiv[4] = { 1, 2, 4, 1 }; - static const char * const get_freq_khz[] = { "core", "ring_osc_60mhz", "run", "cpll", "system_bus" }; @@ -118,10 +116,10 @@ static unsigned long clk_pxa3xx_smemc_get_rate(struct clk_hw *hw, unsigned long parent_rate) { unsigned long acsr = ACSR; - unsigned long memclkcfg = __raw_readl(MEMCLKCFG); return (parent_rate / 48) * smcfs_mult[(acsr >> 23) & 0x7] / - df_clkdiv[(memclkcfg >> 16) & 0x3]; + pxa3xx_smemc_get_memclkdiv(); + } PARENTS(clk_pxa3xx_smemc) = { "spll_624mhz" }; RATE_RO_OPS(clk_pxa3xx_smemc, "smemc"); |