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| author |   Georgi Djakov <georgi.djakov@linaro.org> | 2015-03-20 18:30:26 +0200 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@codeaurora.org> | 2015-03-23 16:09:19 -0700 |
| commit | 293d2e97b37f545bb36aef78cd549d9e6cd66e7f (patch) | |
| tree | 4b8ba1c40d681b198dd67696087cf03531f03ca0 /drivers/clk/qcom/clk-rcg.c | |
| parent | clk: qcom: Do some error handling in configure_bank() (diff) | |
| download | linux-dev-293d2e97b37f545bb36aef78cd549d9e6cd66e7f.tar.xz linux-dev-293d2e97b37f545bb36aef78cd549d9e6cd66e7f.zip | |
clk: qcom: Introduce parent_map tables
In the current parent mapping code, we can get duplicate or inconsistent
indexes, which leads to discrepancy between the number of elements in the
array and the number of parents. Until now, this was solved with some
reordering but this is not always possible.
This patch introduces index tables that are used to define the relations
between the PLL source and the hardware mux configuration value.
To accomplish this, here we do the following:
- Define a parent_map struct to map the relations between PLL source index
and register configuration value.
- Add a qcom_find_src_index() function for finding the index of a clock
matching the specific PLL configuration.
- Update the {set,get}_parent RCG functions use the newly introduced
parent_map struct.
- Convert all existing drivers to the new parent_map tables.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/qcom/clk-rcg.c')
| -rw-r--r-- | drivers/clk/qcom/clk-rcg.c | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/drivers/clk/qcom/clk-rcg.c b/drivers/clk/qcom/clk-rcg.c index 2c5d85961f54..8f2f48071a7a 100644 --- a/drivers/clk/qcom/clk-rcg.c +++ b/drivers/clk/qcom/clk-rcg.c @@ -54,7 +54,7 @@ static u8 clk_rcg_get_parent(struct clk_hw *hw) goto err; ns = ns_to_src(&rcg->s, ns); for (i = 0; i < num_parents; i++) - if (ns == rcg->s.parent_map[i]) + if (ns == rcg->s.parent_map[i].cfg) return i; err: @@ -90,7 +90,7 @@ static u8 clk_dyn_rcg_get_parent(struct clk_hw *hw) ns = ns_to_src(s, ns); for (i = 0; i < num_parents; i++) - if (ns == s->parent_map[i]) + if (ns == s->parent_map[i].cfg) return i; err: @@ -105,7 +105,7 @@ static int clk_rcg_set_parent(struct clk_hw *hw, u8 index) u32 ns; regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns); - ns = src_to_ns(&rcg->s, rcg->s.parent_map[index], ns); + ns = src_to_ns(&rcg->s, rcg->s.parent_map[index].cfg, ns); regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns); return 0; @@ -206,7 +206,7 @@ static u32 mn_to_reg(struct mn *mn, u32 m, u32 n, u32 val) static int configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f) { u32 ns, md, reg; - int bank, new_bank, ret; + int bank, new_bank, ret, index; struct mn *mn; struct pre_div *p; struct src_sel *s; @@ -276,7 +276,10 @@ static int configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f) } s = &rcg->s[new_bank]; - ns = src_to_ns(s, s->parent_map[f->src], ns); + index = qcom_find_src_index(hw, s->parent_map, f->src); + if (index < 0) + return index; + ns = src_to_ns(s, s->parent_map[index].cfg, ns); ret = regmap_write(rcg->clkr.regmap, ns_reg, ns); if (ret) return ret; |