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| author |   Stephen Boyd <sboyd@kernel.org> | 2019-09-04 11:14:51 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2019-09-04 11:14:51 -0700 |
| commit | 924a8c6edaed6152711975a06d5ce73b99c486f9 (patch) | |
| tree | 0b4be4bd5091b398a875f5d0cc75245109bc8e6d /drivers/clk/qcom/clk-rcg2.c | |
| parent | Linus 5.3-rc1 (diff) | |
| parent | clk: sunxi-ng: h6: Allow I2S to change parent rate (diff) | |
| download | linux-dev-924a8c6edaed6152711975a06d5ce73b99c486f9.tar.xz linux-dev-924a8c6edaed6152711975a06d5ce73b99c486f9.zip | |
Merge tag 'sunxi-clk-for-5.4-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner
Pull Allwinner clock changes from Maxime Ripard:
A few patches to enable the V3 SoC and fix the i2s clock for the H6.
* tag 'sunxi-clk-for-5.4-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: h6: Allow I2S to change parent rate
clk: sunxi-ng: v3s: add Allwinner V3 support
clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks
dt-bindings: clk: sunxi-ccu: add compatible string for V3 CCU
clk: sunxi-ng: v3s: add the missing PLL_DDR1
Diffstat (limited to 'drivers/clk/qcom/clk-rcg2.c')
0 files changed, 0 insertions, 0 deletions