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| author |   Taniya Das <tdas@codeaurora.org> | 2019-02-11 13:09:28 +0530 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2019-02-21 14:18:13 -0800 |
| commit | 9d575719ca9b8e177391addb2855be3911dc0d93 (patch) | |
| tree | 67eb504d8ef11b8d81b29922136c9f61c810c9b4 /drivers/clk/qcom/gcc-qcs404.c | |
| parent | clk: qcom: clk-rcg2: Introduce a cfg offset for RCGs (diff) | |
| download | linux-dev-9d575719ca9b8e177391addb2855be3911dc0d93.tar.xz linux-dev-9d575719ca9b8e177391addb2855be3911dc0d93.zip | |
clk: qcom: gcc-qcs404: Add cfg_offset for blsp1_uart3 clock
The CFG/M/N/D registers are at an offset of 0x20 from the CMD register
only for blsp1_uart3 clock, so add it for uart3 only.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Anu Ramanathan <anur@codeaurora.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/qcom/gcc-qcs404.c')
| -rw-r--r-- | drivers/clk/qcom/gcc-qcs404.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c index 64da032bb9ed..493e055299b4 100644 --- a/drivers/clk/qcom/gcc-qcs404.c +++ b/drivers/clk/qcom/gcc-qcs404.c @@ -678,6 +678,7 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = { .cmd_rcgr = 0x4014, .mnd_width = 16, .hid_width = 5, + .cfg_off = 0x20, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_blsp1_uart0_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ |