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| author |   AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> | 2021-01-14 23:10:56 +0100 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2021-02-08 10:24:33 -0800 |
| commit | fa92f3b093d6ca624f42d444d5a206f8724b6bb3 (patch) | |
| tree | 69b223a0791f12c9c737302e3ad31a99fc8d50f3 /drivers/clk/qcom | |
| parent | clk: qcom: gcc-msm8998: Fix Alpha PLL type for all GPLLs (diff) | |
| download | linux-dev-fa92f3b093d6ca624f42d444d5a206f8724b6bb3.tar.xz linux-dev-fa92f3b093d6ca624f42d444d5a206f8724b6bb3.zip | |
clk: qcom: mmcc-msm8998: Add hardware clockgating registers to some clks
Hardware clock gating is supported on some of the clocks declared in
there: ignoring that it does exist may lead to unstabilities on some
firmwares.
Add the HWCG registers where applicable to stop potential crashes.
This was verified on a smartphone shipped with a recent MSM8998
firmware, which will experience random crashes without this change.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Link: https://lore.kernel.org/r/20210114221059.483390-9-angelogioacchino.delregno@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/qcom')
| -rw-r--r-- | drivers/clk/qcom/mmcc-msm8998.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/clk/qcom/mmcc-msm8998.c b/drivers/clk/qcom/mmcc-msm8998.c index dd68983fe22e..0f7c2a48ef2e 100644 --- a/drivers/clk/qcom/mmcc-msm8998.c +++ b/drivers/clk/qcom/mmcc-msm8998.c @@ -1211,6 +1211,8 @@ static struct clk_rcg2 vfe1_clk_src = { static struct clk_branch misc_ahb_clk = { .halt_reg = 0x328, + .hwcg_reg = 0x328, + .hwcg_bit = 1, .clkr = { .enable_reg = 0x328, .enable_mask = BIT(0), @@ -1241,6 +1243,8 @@ static struct clk_branch video_core_clk = { static struct clk_branch video_ahb_clk = { .halt_reg = 0x1030, + .hwcg_reg = 0x1030, + .hwcg_bit = 1, .clkr = { .enable_reg = 0x1030, .enable_mask = BIT(0), @@ -1315,6 +1319,8 @@ static struct clk_branch video_subcore1_clk = { static struct clk_branch mdss_ahb_clk = { .halt_reg = 0x2308, + .hwcg_reg = 0x2308, + .hwcg_bit = 1, .clkr = { .enable_reg = 0x2308, .enable_mask = BIT(0), @@ -2496,6 +2502,8 @@ static struct clk_branch mnoc_ahb_clk = { static struct clk_branch bimc_smmu_ahb_clk = { .halt_reg = 0xe004, + .hwcg_reg = 0xe004, + .hwcg_bit = 1, .clkr = { .enable_reg = 0xe004, .enable_mask = BIT(0), @@ -2511,6 +2519,8 @@ static struct clk_branch bimc_smmu_ahb_clk = { static struct clk_branch bimc_smmu_axi_clk = { .halt_reg = 0xe008, + .hwcg_reg = 0xe008, + .hwcg_bit = 1, .clkr = { .enable_reg = 0xe008, .enable_mask = BIT(0), |