diff options
| author |   Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2020-08-31 19:37:22 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2020-09-04 09:42:01 +0200 |
| commit | e41cb217932969a20cea9c44299c449236058e43 (patch) | |
| tree | 7760f73ebb28b205b2d6eca33a846f06783ef2b8 /drivers/clk/renesas/r8a7790-cpg-mssr.c | |
| parent | clk: renesas: r8a7742: Add clk entry for VSPR (diff) | |
| download | linux-dev-e41cb217932969a20cea9c44299c449236058e43.tar.xz linux-dev-e41cb217932969a20cea9c44299c449236058e43.zip | |
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
VSP1 instances VSPS (which stands for "VSP Standard") and VSPR (which
stands for "VSP for Resizing") were wrongly named as "vsp1-sy" and
"vsp1-rt". The clock section in the SoC datasheets misunderstood the
abbreviations as meaning VSP System and VSP Realtime, and named the
corresponding clocks VSP1(SY) and VSP1(RT). This mistake has been
carried over to the kernel code.
This patch fixes this by renaming the clock names to "vsps" and "vspr".
Inspired from commit 79ea9934b8df ("ARM: shmobile: r8a7790: Rename
VSP1_(SY|RT) clocks to VSP1_(S|R)")
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20200831183722.8165-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas/r8a7790-cpg-mssr.c')
| -rw-r--r-- | drivers/clk/renesas/r8a7790-cpg-mssr.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/renesas/r8a7790-cpg-mssr.c b/drivers/clk/renesas/r8a7790-cpg-mssr.c index c57cb93f8315..f7d233e0c142 100644 --- a/drivers/clk/renesas/r8a7790-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7790-cpg-mssr.c @@ -108,8 +108,8 @@ static const struct mssr_mod_clk r8a7790_mod_clks[] __initconst = { DEF_MOD("tmu0", 125, R8A7790_CLK_CP), DEF_MOD("vsp1du1", 127, R8A7790_CLK_ZS), DEF_MOD("vsp1du0", 128, R8A7790_CLK_ZS), - DEF_MOD("vsp1-rt", 130, R8A7790_CLK_ZS), - DEF_MOD("vsp1-sy", 131, R8A7790_CLK_ZS), + DEF_MOD("vspr", 130, R8A7790_CLK_ZS), + DEF_MOD("vsps", 131, R8A7790_CLK_ZS), DEF_MOD("scifa2", 202, R8A7790_CLK_MP), DEF_MOD("scifa1", 203, R8A7790_CLK_MP), DEF_MOD("scifa0", 204, R8A7790_CLK_MP), |