diff options
| author |   Biju Das <biju.das@bp.renesas.com> | 2018-03-28 20:26:12 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2018-04-16 13:39:40 +0200 |
| commit | 5bf2fbbef50ca521ade4d4fbd366e9273743c503 (patch) | |
| tree | eb60f0f53cb56ef998c6cd8b6b5602d33fde61bc /drivers/clk/renesas/rcar-gen2-cpg.c | |
| parent | clk: renesas: Add r8a77470 CPG Core Clock Definitions (diff) | |
| download | linux-dev-5bf2fbbef50ca521ade4d4fbd366e9273743c503.tar.xz linux-dev-5bf2fbbef50ca521ade4d4fbd366e9273743c503.zip | |
clk: renesas: cpg-mssr: Add r8a77470 support
Add RZ/G1C (R8A77470) Clock Pulse Generator / Module Standby and Software
Reset support.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas/rcar-gen2-cpg.c')
| -rw-r--r-- | drivers/clk/renesas/rcar-gen2-cpg.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/clk/renesas/rcar-gen2-cpg.c b/drivers/clk/renesas/rcar-gen2-cpg.c index feb14579a71b..0c49f59d5074 100644 --- a/drivers/clk/renesas/rcar-gen2-cpg.c +++ b/drivers/clk/renesas/rcar-gen2-cpg.c @@ -16,6 +16,7 @@ #include <linux/init.h> #include <linux/io.h> #include <linux/slab.h> +#include <linux/sys_soc.h> #include "renesas-cpg-mssr.h" #include "rcar-gen2-cpg.h" @@ -261,6 +262,11 @@ static const struct rcar_gen2_cpg_pll_config *cpg_pll_config __initdata; static unsigned int cpg_pll0_div __initdata; static u32 cpg_mode __initdata; +static const struct soc_device_attribute soc_r8a77470[] = { + { .soc_id = "r8a77470" }, + { /* sentinel */ } +}; + struct clk * __init rcar_gen2_cpg_clk_register(struct device *dev, const struct cpg_core_clk *core, const struct cpg_mssr_info *info, struct clk **clks, void __iomem *base, @@ -327,11 +333,17 @@ struct clk * __init rcar_gen2_cpg_clk_register(struct device *dev, case CLK_TYPE_GEN2_SD0: table = cpg_sd01_div_table; + if (soc_device_match(soc_r8a77470)) + table++; + shift = 4; break; case CLK_TYPE_GEN2_SD1: table = cpg_sd01_div_table; + if (soc_device_match(soc_r8a77470)) + table++; + shift = 0; break; |